DS90UA101-Q1 Datasheet, PDF (22/42 Pages) Texas Instruments – DS90UA101-Q1 Multi-Channel Digital Audio Link

DS90UA101-Q1
SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013
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The Serializer switches over to an internal reference clock when SCK is idle or missing. This frequency is
selectable via the device control registers, as shown below (Table 1).
Table 1. Internal Oscillator Frequencies for Forward Channel Frame during Normal Operation
DS90UA101-Q1
Reg 0x14 [2:1]
00
01
10
11
Frequency (MHz)
~25
~50
~25
~12.5
SET Pin on Serializer
The SET pin on the Serializer sets the internal configuration of the part for audio sources with SCK in the range
of 10 MHz to 50MHz. It requires a 10 kΩ pull-up resistor to 1.8V, and a 100 kΩ pull-down resistor to GND. The
recommended resistor tolerance is 1% (Figure 15).
1.8V
10k3
100k3
SET
Serializer
Figure 15. SET Pin configuration on DS90UA101-Q1
Line Rate Calculations for the DS90UA101-Q1/DS90UA102-Q1
The following formula is used to calculate the line rate for the DS90UA101-Q1/DS90UA102-Q1 chipset:
• Line rate = ƒ_SCK * 28
Serial Frame Format
For example, for maximum line rate, ƒ_SCK = 50 MHz, line rate = 50 * 28 = 1.4 Gbps.
The high-speed forward channel is composed of 28 bits of data containing digital audio data, sync signals, I²C
and parity bits. This data payload is optimized for signal transmission over an AC-coupled link. Data is
randomized, balanced and scrambled. The Bidirectional Control Channel data is transferred over the single serial
link along with the high-speed forward data. This architecture provides a full duplex, low-speed control path
across the serial link together with the high speed forward channel.
Serial Audio Formats
There are several de-facto industry standards or formats that define the required alignments and signal polarities
between the left/right clock (LRCK), bit clock (BCK), and the serial audio data. Hence, this section is dedicated to
discussing various serial audio formats.
I²S Format
An I²S bus uses three signal lines for data transfer – a frame or word clock (LRCK), a bit clock (BCK), and a
single or multiple data lines. The device which generates the appropriate BCK and LRCK signals on the bus is
called Master, whereas other devices which accept BCK and LRCK as inputs are all slaves.
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