DS90UA101-Q1 Datasheet, PDF (19/42 Pages) Texas Instruments – DS90UA101-Q1 Multi-Channel Digital Audio Link

DS90UA101-Q1
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Addr
(Hex)
0x0F
Name
Bits
I²C Master Config 7:5
4:3
Field
RSVD
SDA Output
Delay
R/W
RW
2
Local Write
RW
Disable
1
I²C Bus Timer
RW
Speed Up
0
I²C Bus Timer
RW
Disable
0x10 I²C Control
7
RSVD
6:4 I²C SDA Hold
RW
Time
3:0 I²C Filter Depth
RW
0x11 SCL High Time 7:0 SCL High Time
RW
0x12 SCL Low Time 7:0 SCL Low Time
RW
0x13 General Purpose 7:0 GPCR[7:0]
RW
Control
0x14 BIST Control
7:3 RSVD
Clock Source
RW
2:1
0
RSVD
RW
Default
(Hex)
0x00
0x17
0x82
0x82
0x00
0x00
SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013
Description
Reserved.
SDA output delay. This field configures the output delay
on the SDA output. Setting this value will increase the
output delay in units of 50ns. Nominal output delay
values for SCL to SDA are:
00: 350 ns
01: 400 ns
10: 450 ns
11: 500 ns
Disable remote writes to local registers. Setting this bit to
1 will prevent remote writes to local device registers from
across the control channel. This prevents writes to the
Serializer registers from an I²C Master attached to the
Deserializer. Setting this bit does not affect remote
access to I²C slaves at the Serializer.
Speed up I²C bus Watchdog Timer.
1: Watchdog Timer expires after approximately 50
microseconds.
0: Watchdog Timer expires after approximately 1 second.
The I²C Watchdog Timer may be used to detect when the
I²C bus is free or hung up following an invalid termination
of a transaction. If SDA is high and no signaling occurs
for approximately 1 second, the I²C bus is assumed to be
free. If SDA is low and no signaling occurs, the device
will attempt to clear the bus by driving 9 clocks on SCL.
1. Disable the I²C bus Watchdog Timer.
0: Enable the I²C bus Watchdog Timer.
Reserved.
Internal SDA hold time. This field configures the amount
of internal hold time provided for the SDA input relative to
the SCL input. Units are 50ns.
I²C glitch filter depth. This field configures the maximum
width of glitch pulses on the SCL and SDA inputs that will
be rejected. Units are 10 ns.
I²C Master SCL high time. This field configures the high
pulse width of the SCL output when the Serializer is the
Master on the local I²C bus. Units are 50 ns for the
nominal oscillator clock frequency. The default value is
set to satisfy a minimum (4µs + 1µs of rise time for cases
where rise time is very fast) SCL high time with the
internal oscillator clock running at 26 MHz rather than the
nominal 20MHz.
I²C Master SCL low time. This field configures the low
pulse width of the SCL output when the Serializer is the
Master on the local I²C bus. This value is also used as
the SDA setup time by the I²C slave for providing data
prior to releasing SCL during accesses over the
Bidirectional Control Channel. Units are 50 ns for the
nominal oscillator clock frequency. The default value is
set to satisfy a minimum (4.7µs + 0.3µs of fall time for
cases where fall time is very fast) SCL low time with the
internal oscillator clock running at 26 MHz rather than the
nominal 20MHz.
Scratch register. Used to write and read 8 bits.
Reserved.
Allows the choosing of different internal oscillator clock
frequencies for forward channel frame.
The internal oscillator clock frequency is used when SCK
is idle or missing. See Table 1 for these settings.
Reserved.
Copyright © 2013, Texas Instruments Incorporated
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