DS90UA101-Q1 Datasheet, PDF(31/42 Page) Texas Instruments – DS90UA101-Q1 Multi-Channel Digital Audio Link

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DS90UA101-Q1 Datasheet, PDF (31/42 Pages) Texas Instruments – DS90UA101-Q1 Multi-Channel Digital Audio Link

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DS90UA101-Q1

www.ti.com

SNLS441A â JULY 2013 â REVISED SEPTEMBER 2013

Table 3. BIST Pin Configuration on DS90UA102-Q1 Deserializer(1)

DS90UA102-Q1 Deserializer GPIO[3:2]

Oscillator Source

External

Internal

BIST Frequency (MHz)

SCK

~25

~50

~12.5

(1) Note: These pin settings will only be active when 0x24[3] = 1 and BIST is on.

The BIST mode provides various options for the clock source. Either external pins (GPIO3 and GPIO2 of DES)

or register 0x24 on DES can be used to configure the BIST to use SCK or various internal oscillator frequencies

as the clock source. Refer to Table 4 below for BIST register settings.

Table 4. BIST Register Configuration on DS90UA102-Q1 Deserializer(1)

DS90UA102-Q1 Deserializer 0x24[2:1]

Oscillator Source

External

Internal

BIST Frequency (MHz)

SCK

~50

~25

~12.5

(1) Note: These register settings will only be active when 0x24[3] = 0 and BIST is on.

The BIST status can be monitored real-time on the PASS pin. For every frame with error(s), the PASS pin

toggles low momentarily. If two consecutive frames have errors, PASS will toggle twice to allow counting of

frames with errors. Once the BIST is done, the PASS pin reflects the pass/fail status momentarily (pass = no

errors, fail = one or more errors). The BIST result can also be read through I2C for the number of frames that

errored. The status register retains results until it is reset by a new BIST session or a device reset. For all

practical purposes, the BIST status can be monitored from the BIST Error Count register 0x25 on the

DS90UA102-Q1 Deserializer.

Sample BIST Sequence (Refer to Figure 28)

Step 1: BIST mode is enabled via the BISTEN pin on the DS90UA102-Q1 Deserializer, or through the

Deserializer control registers. The clock source is selected through the GPIO3 and GPIO2 pins as shown in

Table 3.

Step 2: The DS90UA101-Q1 Serializer BIST start command is activated through the back channel.

Step 3: The BIST pattern is generated and sent through the serial interface to the Deserializer. Once the

Serializer and Deserializer are in the BIST mode and the Deserializer acquires LOCK, the PASS pin of the

Deserializer goes high and BIST starts checking the data stream. If an error in the payload is detected the PASS

pin will switch low momentarily. During the BIST test, the PASS output can be monitored and counted to

determine the payload error rate.

Step 4: To stop the BIST mode, the Deserializer BISTEN pin is set low and the Deserializer stops checking the

data. The final test result is not maintained on the PASS pin. To check the number of BIST errors, check the

BIST Error Count register, 0x25 on the Deserializer. The link returns to normal operation after the Deserializer

BISTEN pin is low.

Figure 29 below shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and

Case 2 shows one with multiple errors. In most cases, it is difficult to generate errors due to the robustness of

the link (differential data transmission, adaptive equalization, etc.), thus they may be introduced by greatly

extending the cable length, increasing the frequency, or by reducing signal condition enhancements (Rx

equalization).

Product Folder Links: DS90UA101-Q1

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