BQ4050 Datasheet, PDF (44/53 Pages) Texas Instruments – CEDV Gas Gauge and Protection Solution

bq4050
SLUSC67A – MARCH 2016 – REVISED MARCH 2016
Layout Guidelines (continued)
www.ti.com
Figure 46. Sense Resistor, Ground Shield, and Filter Circuit Layout
10.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
The general principle is to use wide copper traces to lower the inductance of the bypass capacitor circuit. In
Figure 47, an example layout demonstrates this technique.
Figure 47. Use Wide Copper Traces to Lower the Inductance of Bypass Capacitors C1, C2, and C3
10.1.2 ESD Spark Gap
Protect SMBus Clock, Data, and other communication lines from ESD with a spark gap at the connector. The
pattern in Figure 48 recommended, with 0.2-mm spacing between the points.
44
Submit Documentation Feedback
Product Folder Links: bq4050
Copyright © 2016, Texas Instruments Incorporated