BQ4050 Datasheet, PDF (12/53 Pages) Texas Instruments – CEDV Gas Gauge and Protection Solution

bq4050
SLUSC67A – MARCH 2016 – REVISED MARCH 2016
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6.16 Electrical Characteristics: ADC
Typical values stated where T_A = 25°C and VCC = 14.4 V, Min/Max values stated where T_A = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Input voltage range
Full scale range
Integral nonlinearity⁽¹⁾
Offset error⁽²⁾
Offset error drift
Gain error
Gain error drift
Effective input resistance
Internal reference (V_REF1)
External reference (V_REG)
V_FS = V_REF1 or V_REG
16-bit, best fit, –0.1 V to 0.8 x V_REF1
16-bit, best fit, –0.2 V to –0.1 V
16-bit, Post-calibration, V_FS = V_REF1
16-bit, Post-calibration, V_FS = V_REF1
16-bit, –0.1 V to 0.8 x V_FS
16-bit, –0.1 V to 0.8 x V_FS
–0.2
–0.2
–V_FS
8
±67
0.6
±0.2%
1
0.8 x V_REG
V_FS
±6.6
±13.1
±157
3
±0.8%
150
V
V
LSB
µV
µV/°C
FSR
PPM/°C
MΩ
(1) 1 LSB = V_REF1/(2^N) = 1.225/(2¹⁵) = 37.4 µV (when t_CONV = 31.25 ms)
(2) For VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3, VC4–VSS, PACK–VSS, and V_REF1/2, the offset error is multiplied by (1/ADC
multiplexer scaling factor (K)).
6.17 Electrical Characteristics: ADC Digital Filter
Typical values stated where T_A = 25°C and VCC = 14.4 V, Min/Max values stated where T_A = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Single conversion
31.25
Conversion time
Single conversion
Single conversion
15.63
ms
7.81
Single conversion
1.95
Resolution
No missing codes
16
Bits
Effective resolution
With sign, t_CONV = 31.25 ms
With sign, t_CONV = 15.63 ms
With sign, t_CONV = 7.81 ms
With sign, t_CONV = 1.95 ms
14
15
13
14
Bits
11
12
9
10
6.18 Electrical Characteristics: CHG, DSG FET Drive
Typical values stated where T_A = 25°C and VCC = 14.4 V, Min/Max values stated where T_A = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Output voltage
ratio
Ratio_DSG = (V_DSG – V_BAT)/V_BAT, 2.2 V < V_BAT < 4.92 V,
10 MΩ between PACK and DSG
Ratio_CHG = (V_CHG – V_BAT)/V_BAT, 2.2 V < V_BAT < 4.92 V,
10 MΩ between BAT and CHG
2.133
2.133
2.333
2.333
2.433
—
2.433
V_(FETON)
Output voltage,
V_DSG(ON) = V_DSG – V_BAT, 4.92 V ≤ V_BAT ≤ 18 V, 10 MΩ
between PACK and DSG
CHG and DSG on _{VCHG(ON) = VCHG – VBAT, 4.92 V ≤ VBAT ≤ 18 V, 10 MΩ}
between BAT and CHG
10.5
11.5
10.5
11.5
12
V
12
V_(FETOFF)
t_R
Output voltage,
V_DSG(OFF) = V_DSG – V_PACK, 10 MΩ between PACK and
DSG
CHG and DSG off
V_CHG(OFF) = V_CHG – V_BAT, 10 MΩ between BAT and CHG
Rise time
V_DSG from 0% to 35% V_DSG(ON)(TYP), V_BAT ≥ 2.2 V, C_L =
4.7 nF between DSG and PACK, 5.1 kΩ between DSG
and C_L, 10 MΩ between PACK and DSG
V_CHG from 0% to 35% V_CHG(ON)(TYP), V_BAT ≥ 2.2 V, C_L =
4.7 nF between CHG and BAT, 5.1 kΩ between CHG
and C_L, 10 MΩ between BAT and CHG
–0.4
–0.4
200
200
0.4
V
0.4
500
µs
500
12
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