TCA6408A-Q1 Datasheet, PDF (4/40 Pages) Texas Instruments – Low-Voltage 8-Bit I2C and SMBus I/O Expander With Interrupt Output

TCA6408A-Q1
SCPS234 – SEPTEMBER 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (see ⁽¹⁾)
V_CCI
V_CCP
V_I
V_O
I_IK
I_OK
I_IOK
I_OL
I_OH
I_CC
T_j(MAX)
T_stg
Supply voltage for I²C pins
Supply voltage for P-ports
Input voltage⁽²⁾
Output voltage⁽²⁾
Input clamp current
Output clamp current
Input/output clamp current
Continuous output low current
Continuous output low current
Continuous output high current
Continuous current through GND
Continuous current through V_CCP
Continuous current through V_CCI
Maximum junction temperature
Storage temperature
ADDR, RESET, SCL
INT
P-port
SDA
P-port
SDA, INT
P-port
V_I < 0
V_O < 0
V_O < 0 or V_O > V_CCP
V_O < 0 or V_O > V_CCI
V_O = 0 to V_CCP
V_O = 0 to V_CCI
V_O = 0 to V_CCP
MIN
MAX
UNIT
–0.5
3.6
V
–0.5
3.6
V
–0.5
3.6
V
–0.5
3.6
V
±20
mA
±20
mA
±20
mA
±20
50
mA
25
50
mA
200
160
mA
10
135
°C
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
V_(ESD) Electrostatic discharge
Human body model (HBM), per AEC Q100-002⁽¹⁾
Charged-device model (CDM), per AEC Q100-011
VALUE
±2000
±1000
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
UNIT
V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
V_CCI ⁽¹⁾
V_CCP
V_IH
V_IL
I_OH
Supply voltage for I²C pins
Supply voltage for P-ports
High-level input voltage
Low-level input voltage
High-level output current
SCL, SDA, INT
P-ports, ADDR, RESET
SCL, SDA
RESET
ADDR, P7–P0
SCL, SDA, RESET
ADDR, P7–P0
P00-P07
MIN
MAX
1.65
3.6
1.65
3.6
0.7 × V_CCI
0.7 × V_CCI
0.7 × V_CCP
–0.5
–0.5
V_CCI
3.6
3.6
0.3 × V_CCI
0.3 × V_CCP
10
UNIT
V
V
V
V
mA
(1) For voltages applied above V_CCI, and increase in I_CC will result.
4
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