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TCA6408A-Q1 Datasheet, PDF (24/40 Pages) Texas Instruments – Low-Voltage 8-Bit I2C and SMBus I/O Expander With Interrupt Output
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TCA6408A-Q1
SCPS234 – SEPTEMBER 2016
www.ti.com
8.6.3 Register Descriptions
The Input Port Register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration Register. They act only on read operation. Writes to this
register have no effect. The default value (X) is determined by the externally applied logic level. Before a read
operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port
Register will be accessed next. See Table 5.
BIT
DEFAULT
Table 5. Register 0 (Input Port Register)
I-7
I-6
I-5
I-4
I-3
I-2
I-1
I-0
X
X
X
X
X
X
X
X
The Output Port Register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration Register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. See
Table 6.
BIT
DEFAULT
Table 6. Register 1 (Output Port Register)
O-7
O-6
O-5
O-4
O-3
O-2
O-1
O-0
1
1
1
1
1
1
1
1
The Polarity Inversion Register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
Register. If a bit in this register is set (written with 1), the polarity of the corresponding port pin is inverted. If a bit
in this register is cleared (written with a 0), the original polarity of the corresponding port pin is retained. See
Table 7.
Table 7. Register 2 (Polarity Inversion Register)
BIT
DEFAULT
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N-0
0
0
0
0
0
0
0
0
The Configuration Register (register 3) configures the direction of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output. See Table 8.
BIT
DEFAULT
Table 8. Register 3 (Configuration Register)
C-7
C-6
C-5
C-4
C-3
C-2
C-1
C-0
1
1
1
1
1
1
1
1
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