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TCA6408A-Q1 Datasheet, PDF (31/40 Pages) Texas Instruments – Low-Voltage 8-Bit I2C and SMBus I/O Expander With Interrupt Output
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11 Layout
TCA6408A-Q1
SCPS234 – SEPTEMBER 2016
11.1 Layout Guidelines
For printed circuit board (PCB) layout of the TCA6408A-Q1, common PCB layout practices must be followed, but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs are
not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCCI and VCCP pins, using a larger capacitor to provide
additional power in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency
ripple. These capacitors must be placed as close to the TCA6408A-Q1 as possible. These best practices are
shown in Layout Example.
For the layout example provided in Layout Example, it is possible to fabricate a PCB with only 2 layers by using
the top layer for signal routing and the bottom layer as a split plane for power (VCCI and VCCP) and ground (GND).
However, a 4-layer board is preferable for boards with higher density signal routing. On a 4-layer PCB, it is
common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate
the other internal layer to a power plane. In a board layout using planes or split planes for power and ground,
vias are placed directly next to the surface mount component pad which needs to attach to VCCI, VCCP, or GND
and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when a
signal trace needs to be routed to the opposite side of the board, but this technique is not demonstrated in
Layout Example.
11.2 Layout Example
= Via to GND Plane
To CPU/MCU
V CCI
ADDR
V CCP
SDA
RST
SCL
P0
IN T
TCA6408A-Q1
P1
P7
P2
P6
P3
P5
GND
P4
Figure 40. Example Layout (PW Package)
Copyright © 2016, Texas Instruments Incorporated
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