TCA6408A-Q1 Datasheet, PDF (29/40 Pages) Texas Instruments – Low-Voltage 8-Bit I2C and SMBus I/O Expander With Interrupt Output

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10 Power Supply Recommendations
TCA6408A-Q1
SCPS234 – SEPTEMBER 2016
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA6408A-Q1 can be reset to its default conditions by using the
power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset.
This reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 36 and Figure 37.
V_CCP
Ramp-Up
Ramp-Down
Re-Ramp-Up
t_{RR_GND}
Time
Time to Re-Ramp
t _RT
t _FT
t _RT
Figure 36. V_CCP is Lowered Below 0.2 V and then Ramped Up to V_CCP
V_CCP
V_IN drops below POR levels
Ramp-Down
t _{RR_POR50}
Ramp-Up
Time to Re-Ramp
t _FT
t _RT
Time
Figure 37. V_CCP is Lowered Below the POR Threshold, then Ramped Back Up to V_CCP
Table 9 specifies the performance of the power-on reset feature for TCA6408A-Q1 for both types of power-on
reset.
Table 9. Recommended Supply Sequencing and Ramp Rates at T_A = 25°C⁽¹⁾
t_FT
t_RT
t_{RR_GND}
t_{RR_POR50}
V_{CCP_GH}
V_{CCP_MV}
t_{VCCP_GW}
V_PORF
V_PORR
PARAMETER
Fall rate
Rise rate
Time to re-ramp (when V_CCP drops to GND)
Time to re-ramp (when V_CCP drops to V_{POR_MIN} – 50 mV)
Level that V_CCP can glitch down from V_CCP, but not cause a
functional disruption when t_{VCCP_GW} = 1 μs
The minimum voltage that VCC can glitch down to without
causing a reset (V_{CC_GH} must not be violated)
Glitch width that does not cause a functional disruption when
t_{VCCP_GH} = 0.5 × V_CCx
Voltage trip point of POR on falling V_CCP
Voltage trip point of POR on rising V_CCP
See Figure 36
See Figure 36
See Figure 36
See Figure 37
See Figure 38
See Figure 38
See Figure 38
MIN TYP
0.1
0.1
1
1
1.5
0.6
1
1.2
(1) Not tested. Specified by design.
MAX
2000
2000
1.2
10
1.5
UNIT
ms
ms
μs
μs
V
V
μs
V
V
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