TCA6408A-Q1 Datasheet, PDF (22/40 Pages) Texas Instruments – Low-Voltage 8-Bit I2C and SMBus I/O Expander With Interrupt Output

TCA6408A-Q1
SCPS234 – SEPTEMBER 2016
www.ti.com
Programming (continued)
8.5.2.2 Reads
Reading from a slave is very similar to writing, but requires some additional steps. In order to read from a slave,
the master must first instruct the slave which register it wishes to read from. This is done by the master starting
off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0
(signifying a write), followed by the register address it wishes to read from. When the slave acknowledges this
register address, the master sends a START condition again, followed by the slave address with the R/W bit set
to 1 (signifying a read). This time, the slave acknowledges the read request, and the master releases the SDA
bus but continues supplying the clock to the slave. During this part of the transaction, the master becomes the
master-receiver, and the slave becomes the slave-transmitter.
The master continues to send out the clock pulses, but releases the SDA line so that the slave can transmit data.
At the end of every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for
more data. When the master has received the number of bytes it is expecting, it sends a NACK, signaling to the
slave to halt communications and release the bus. The master follows this up with a STOP condition.
Read transactions that are performed without writing to the address of the device and simply supply the
command byte will result in a NACK.
Figure 27 and Figure 28 show an example of reading a single byte from a slave register.
Master controls SDA line
Slave controls SDA line
Read from one register in a device
Device (Slave) Address (7 bits)
Register Address N (8 bits)
Device (Slave) Address (7 bits)
Data Byte from Register N (8 bits)
S
0
1
0
0
0
0
AD
DR
0
A B7 B6 B5 B4 B3 B2 B1 B0 A Sr
0
1
0
0
0
0
AD
DR
1
A D7 D6 D5 D4 D3 D2 D1 D0 NA P
START
R/W=0 ACK
ACK Repeated START
R/W=1 ACK
Figure 27. Read from Register
NACK STOP
SCL
12 345 67R9
Slave Address
Data From Port
Data From Port
SDA
Read From
Port
S0
1 00
0
0
AD
DR
1
A
Data 1
Start
Condition
R/W
ACK From
Slave
A
Data 4
NA P
ACK From
Master
NACK From
Master
Stop
Condition
Data Into
Port
Data 2
Data 3
Data 4
t_ph
t_ps
Data 5
INT is cleared
by Read from Port
INT
t_iv
t_ir
Stop not needed
to clear INT
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port Register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P-port (see Figure 27).
Figure 28. Read from Input Port Register
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