TCA6408A-Q1 Datasheet, PDF (23/40 Pages) Texas Instruments – Low-Voltage 8-Bit I2C and SMBus I/O Expander With Interrupt Output

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8.6 Register Map
8.6.1 Device Address
The address of the TCA6408A-Q1 is shown in Figure 29.
Slave Address
01
0
0
0
0
AD
DR
R/W
Fixed
Programmable
Figure 29. TCA6408A-Q1 Address
TCA6408A-Q1
SCPS234 – SEPTEMBER 2016
Table 3 shows the TCA6408A-Q1 address reference.
ADDR
L
H
Table 3. Address Reference
I²C BUS SLAVE ADDRESS
32 (decimal), 20 (hexadecimal)
33 (decimal), 21 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
8.6.2 Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte (see
Table 4), which is stored in the Control Register in the TCA6408A-Q1. Two bits of this data byte state both the
operation (read or write) and the internal registers (Input, Output, Polarity Inversion, or Configuration) that is
affected. This register can be written or read through the I²C bus. The command byte is sent only during a write
transmission. See Figure 30.
B7 B6 B5 B4 B3 B2 B1 B0
Figure 30. Control Register Bits
Table 4. Command Byte
CONTROL REGISTER BITS
B7 B6 B5 B4 B3 B2 B1 B0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
COMMAND
BYTE
(HEX)
00
01
02
03
REGISTER
PROTOCOL
POWER-UP
DEFAULT
Input Port
Output Port
Polarity Inversion
Configuration
Read byte
Read/write byte
Read/write byte
Read/write byte
xxxx xxxx
1111 1111
0000 0000
1111 1111
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