SN74AUP1G80_17 Datasheet, PDF (4/38 Pages) Texas Instruments – Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop

SN74AUP1G80
SCES593F – JULY 2004 – REVISED JULY 2017
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
V_CC
Supply voltage
V_I
Input voltage⁽²⁾
V_O
Voltage range applied to any output in the high-impedance or power-off state⁽²⁾
V_O
Voltage range applied to any output in the high or low state⁽²⁾
I_IK
Input clamp current
V_I < 0
I_OK
Output clamp current
V_O < 0
I_O
Continuous output current
Continuous current through V_CC or GND
T_J
Junction temperature
T_stg
Storage temperature
MIN
MAX
UNIT
–0.5
4.6
V
–0.5
4.6
V
–0.5
4.6
V
–0.5
V_CC + 0.5
V
–50
mA
–50
mA
±20
mA
±50
mA
150
°C
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
V_(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾
VALUE
2000
1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
6.3 Recommended Operating Conditions
See ⁽¹⁾
V_CC
Supply voltage
V_IH
High-level input voltage
V_IL
Low-level input voltage
V_I
Input voltage
V_O
Output voltage
I_OH
High-level output current⁽²⁾
V_CC = 0.8 V
V_CC = 1.1 V to 1.95 V
V_CC = 2.3 V to 2.7 V
V_CC = 3 V to 3.6 V
V_CC = 0.8 V
V_CC = 1.1 V to 1.95 V
V_CC = 2.3 V to 2.7 V
V_CC = 3 V to 3.6 V
V_CC = 0.8 V
V_CC = 1.1 V
V_CC = 1.4 V
V_CC = 1.65
V_CC = 2.3 V
V_CC = 3 V
MIN
0.8
V_CC
0.65 × V_CC
1.6
2
0
0
MAX
3.6
0
0.35 × V_CC
0.7
0.9
3.6
V_CC
–20
–1.1
–1.7
–1.9
–3.1
–4
UNIT
V
V
V
V
V
µA
mA
(1) All unused inputs of the device must be held at V_CC or GND to assure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
(2) Defined by the signal integrity requirements and design-goal priorities.
4
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