SN74AUP1G80_17 Datasheet, PDF (3/38 Pages) Texas Instruments – Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop

www.ti.com
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
D
1
5
V_CC
CLK
2
GND
3
4
Q
SN74AUP1G80
SCES593F – JULY 2004 – REVISED JULY 2017
DCK Package
5-Pin SC70
Top View
D
1
5
V_CC
CLK
2
GND
3
4Q
DRY Package
6-Pin SON
Top View
D¹
CLK ²
GND ³
6V
CC
5 _NC
4Q
DSF Package
6-Pin SON
Top View
D¹
CLK ²
GND ³
6V
CC
5 _N.C.
4_Q
YFP Package
6-Pin DSBGA
Bottom View
1
2
C _{GND Q}
B _{CLK N.C.}
A
D
VCC
Not to scale
(1) Preview only
NAME
D
CLK
GND
Q
NC
V_CC
DBV,
DCK
1
2
3
4
—
5
PIN
DRY, DSF YFP
1
A1
2
B1
3
C1
4
C2
5
B2
6
A2
DPW Package⁽¹⁾
5-Pin X2SON
Top View
D
GND
V_CC
CLK
Q
YZP Package
5-Pin DSBGA
Bottom View
1
2
C _{GND Q}
B _CLK
A
D
VCC
Not to scale
Pin Functions
I/O
YZP
DPW
DESCRIPTION
A1
1
I Data input
B1
2
I Positive-Edge-Triggered Clock input
C1
3
— Ground pin
C2
4
O Inverted output
—
—
— No Internal Connection
A2
5
— Positive Supply
Copyright © 2004–2017, Texas Instruments Incorporated
Product Folder Links: SN74AUP1G80
Submit Documentation Feedback
3