SN74AUP1G80_17 Datasheet, PDF (16/38 Pages) Texas Instruments – Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop

SN74AUP1G80
SCES593F – JULY 2004 – REVISED JULY 2017
9 Application and Implementation
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NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A useful application for the SN74AUP1G80 is using it as a frequency divider. By feeding back the output (Q) to
the input (D), the output toggles on every rising edge of the clock waveform. The output goes HIGH once every
two clock cycles, so essentially the frequency of the clock signal is divided by a factor of two. The device does
not have preset or clear functions so the initial state of the output is unknown. This application implements the
use of an override pin to initially set the input HIGH or LOW. Initialization is not needed, but should be kept in
mind. Post initialization, the Override input is set to a high-impedance mode, or it can be used to force a HIGH or
LOW output.
9.2 Typical Application
10 k
Override
1D
1.65 - 5.5V
VCC 5
0.1 F
1 kHz Clock
2 CLK
3 GND
Q4
500 Hz
Clock
Figure 7. Clock Frequency Division
9.2.1 Design Requirements
For this application, a resistor must be placed on the feedback line in order for the initialization voltage from the
override input to overpower the signal coming from the output (Q). Without a resistor the state at the input would
be unknown as the output of the SN74AUP1G80 is driving the line separate from the Override input.
The SN74AUP1G80 device uses CMOS technology and has balanced output drive. Take care to avoid bus
contention because it can drive currents that would exceed maximum limits.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– For rise time and fall time specifications, see Δt/Δv in Recommended Operating Conditions.
– For specified high and low levels, see V_IH and V_IL in Recommended Operating Conditions.
– Input voltages are recommended to not go below 0 V and not exceed 4.6 V for any V_CC. See Absolute
Maximum Ratings.
2. Recommended output conditions:
– Load currents should not exceed ±20 mA. See Absolute Maximum Ratings.
– Output voltages are recommended to not go below 0 V and not exceed the V_CC voltage. See Absolute
Maximum Ratings.
3. Feedback resistor:
– A 10-kΩ resistor is chosen to bias the input so the Override input can initialize the input and output. The
resistor value is important because a resistance too high, such as 1 MΩ, would cause too much of a
voltage drop, causing the output to no longer be able to drive the input. On the other hand, a resistor too
low, such as a 1 Ω, would not bias enough and might cause bus contention between the Q output and the
override input, possibly damaging the device.
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