DS90UA101-Q1_14 Datasheet, PDF (36/41 Pages) Texas Instruments – Multi-Channel Digital Audio Link

DS90UA101-Q1
SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013
www.ti.com
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise
effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In
some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four-layer board with a power and ground plane. Locate LVCMOS signals away from the
differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential
lines of 100Ω are typically recommended for differential interconnect. The closely coupled lines help to ensure
that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines
will also radiate less.
Information on the LLP style package is provided in TI Application Note 1187.
Interconnect Guidelines
See AN-1108 and AN-905 for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– – S = space between the pair
– – 2S = space between pairs
– – 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500 Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas
Instrument web site at: www.ti.com/lvds.
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