DS90UA101-Q1_14 Datasheet, PDF (30/41 Pages) Texas Instruments – Multi-Channel Digital Audio Link

DS90UA101-Q1
SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013
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General Purpose Inputs, Outputs (GPIs, GPOs, GPIOs) Descriptions
There are 4 dedicated general purpose inputs (GPIs) on the DS90UA101-Q1 and 4 dedicated general purpose
outputs (GPOs) on the DS90UA102-Q1. Inputs to the GPI pins on the Serializer are fed to the GPO outputs on
the Deserializer. The maximum GPI data rate is defined by the SCK source (up to 50 Mbps).
In addition, there are also 4 GPOs on the DS90UA101-Q1 and 4 GPIOs on the DS90UA102-Q1. The GPOs on
the Serializer can be configured as outputs for the input signals that are fed into the Deserializer GPIOs. The
GPIO maximum data rate is up to 66 kbps when configured for communication between Deserializer GPIO to
Serializer GPO. Both the GPOs on the Serializer and GPIOs on the Deserializer can also behave as outputs
whose values are set from local registers.
LVCMOS V_DDIO Option
1.8V/3.3V Serializer inputs are user configurable to provide compatibility with 1.8V and 3.3V system interfaces.
Power Up Requirements and PDB Pin
The Serializer is active when the PDB pin is driven HIGH. Driving the PDB pin LOW powers down the device and
clears all control register configurations to default values. The PDB pin must be held low until the power supplies
(V_DDn and V_DDIO) have settled to the recommended operating voltage. This can be done by driving PDB
externally, or an RC network can be connected to the PDB pin to ensure PDB arrives after all the power supplies
have stabilized.
Powerdown
The PDB pin's function on the Serializer is to ENABLE or powerdown the device. This pin can be controlled by
the system and can be used to disable the SER to save power. If PDB = HIGH, the SER will lock to the valid
input SCK and transmit data to the DES by sending a serial stream at 28 times the SCK frequency. If SCK is idle
or missing, the SER will output a serial stream based on its internal oscillator frequency (Table 1). When PDB =
LOW, the high-speed driver outputs are static HIGH.
SCK Clock Edge Select (TRFB)
The TRFB selects which edge of the input clock is used to latch input data. If TRFB register is 1, data is latched
on the rising edge of the SCK. If TRFB register is 0, data is latched on the falling edge of the SCK.
SCK
DIN
TRFB: 0
TRFB: 1
Figure 27. Programmable SCK Strobe Select
Built In Self Test (BIST)
An optional at-speed built in self test (BIST) feature supports the testing of the high speed serial link and low-
speed back channel. This is useful in the prototype stage, equipment production, and in-system test and also for
system diagnostics.
BIST Configuration and Status
The DS90UA101-Q1/DS90UA102-Q1 chipset can be programmed into BIST mode using either pins or registers.
By default BIST configuration is controlled through pins on the DS90UA102-Q1. BIST can also be configured via
registers using BIST Control Register 0x24 on the DS90UA102-Q1. Pin based configuration is defined as follows:
• BISTEN (on DS90UA102-Q1) = HIGH: Enable the BIST mode, BISTEN = LOW: Disable the BIST mode.
• GPIO3 and GPIO2 of DS90UA102-Q1: Defines the BIST clock source (SCK vs. various internal oscillator
frequencies). See Table 3 below.
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