DS90UA101-Q1_14 Datasheet, PDF (15/41 Pages) Texas Instruments – Multi-Channel Digital Audio Link

DS90UA101-Q1
www.ti.com
DS90UA101-Q1 REGISTER INFORMATION
SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013
The table below contains information on the DS90UA101-Q1 control registers. These registers are accessible
locally via the I²C control interface, or remotely via the Bidirectional Control Channel. Addresses not listed are
reserved. Fields listed as reserved should not be changed from the listed default value.
Addr
(Hex)
0x00
Name
I²C Device ID
Bits Field
7:1 DEVICE ID
Default
R/W
(Hex)
Description
RW
0xB0 7-bit address of Serializer.
0x58'h (0101_100X'b) default.
0
SER ID SEL
RW
0: Serializer DEVICE ID is from IDx.
1: Register I²C DEVICE ID overrides IDx.
0x01 Power and Reset 7
RSVD
0x30 Reserved.
6
RDS
RW
Digital output drive strength.
1: High drive strength.
0: Low drive strength.
5
V_DDIO Control
RW
Auto voltage control.
1: Enable (auto-detect mode).
0: Disable.
4
V_DDIO Mode
RW
3
ANAPWDN
RW
V_DDIO voltage set.
1: Sets V_DDIO mode to 3.3V.
0: Sets V_DDIO mode to 1.8V.
This register can be set only through local I²C access.
1: Analog power-down: Powers down the analog block in
the Serializer.
0: Analog power-up: Powers up the analog block in the
Serializer.
2
RSVD
Reserved.
1
Digital Reset 1 RW
1: Resets the digital block except for register values. This
bit is self-clearing.
0: Normal operation.
0
Digital Reset 0 RW
1: Resets the entire digital block including all register
values. This bit is self-clearing.
0: Normal operation.
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: DS90UA101-Q1
Submit Documentation Feedback
15