DS90UA101-Q1_14 Datasheet, PDF (11/41 Pages) Texas Instruments – Multi-Channel Digital Audio Link

DS90UA101-Q1
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SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013
BIDIRECTIONAL CONTROL BUS TIMING SPECIFICATIONS
Bidirectional Control Bus: AC Timing Specifications (SCL, SDA) - I²C Compliant
Over recommended supply and temperature ranges unless otherwise specified. (Figure 4)
Symbol
Parameter
Conditions
Min
Recommended Input Timing Requirements
f_SCL
SCL Clock Frequency
Standard Mode
Fast Mode
Standard Mode
4.7
t_LOW
SCL Low Period
Fast Mode
1.3
Standard Mode
4.0
t_HIGH
SCL High Period
Fast Mode
0.6
t_HD:STA
Hold time for a start or a repeated start ^{Standard Mode}
condition
Fast Mode
4.0
0.6
t_SU:STA
Set Up time for a start or a repeated
start condition
Standard Mode
Fast Mode
4.7
0.6
Standard Mode
0
t_HD:DAT Data Hold Time
Fast Mode
0
Standard Mode
250
t_SU:DAT Data Set Up Time
Fast Mode
100
Standard Mode
4.0
t_SU:STO Set Up Time for STOP Condition
Fast Mode
0.6
Standard Mode
4.7
t_BUF
Bus Free time between Stop and Start
Fast Mode
1.3
t_r
SCL & SDA Rise Time
Standard Mode
Fast Mode
t_f
SCL & SDA Fall Time
Standard Mode
Fast Mode
Typ
Max
Units
100
kHz
400
kHz
µs
µs
µs
µs
µs
µs
µs
µs
3.45
µs
900
ns
ns
ns
µs
µs
µs
µs
1000
ns
300
ns
300
ns
300
ns
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