TMS320C6472_16 Datasheet, PDF (33/269 Pages) Texas Instruments – TMS320C6472 Fixed-Point Digital Signal Processor

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TMS320C6472
SPRS612G – JUNE 2009 – REVISED JULY 2011
Table 2-5. Terminal Functions (continued)
SIGNAL
NAME
TYPE⁽¹⁾ IPD/IPU^{(2) (3)}
NO.
DESCRIPTION
UNIVERSAL TEST AND OPERATIONS PHY INTERFACE FOR ASYNCHRONOUS TRANSFER MODE (ATM) [UTOPIA]
URCLK
J29
I
IPD
Source clock for UTOPIA receive driven by Master ATM
Controller.
URCLAV
J28
O/Z
Receive cell available status output signal from UTOPIA Slave.
0 indicates NO space is available to receive a cell from Master
IPD
ATM Controller.
1 indicates space is available to receive a cell from Master ATM
Controller.
URADDR0
Y29
URADDR1
Y28
URADDR2
Y27
I
IPD
UTOPIA receive address bus
URADDR3
Y26
URADDR4
Y25
URDATA0
AA29
URDATA1
AA28
URDATA2
AA27
URDATA3
AB27
URDATA4
AB26
URDATA5
AB25
URDATA6
AC29
URDATA7
URDATA8
AC28
I
AC27
IPD
UTOPIA 16-bit receive data bus (also supports 8-bit mode on pins
[7:0])
URDATA9
AC26
URDATA10
AC25
URDATA11
AD29
URDATA12
AD28
URDATA13
AD27
URDATA14
AF29
URDATA15
AD26
URENB
AE27
I
UTOPIA receive interface enable input signal. Asserted by the
IPU
Master ATM Controller to indicate to the UTOPIA slave to receive
one or more cells on the URDATA bus with URSOC active on the
first data cycle.
URSOC
AA25
I
Receive start-of-cell signal. This signal is output by the Master
IPD
ATM Controller to indicate to the UTOPIA Slave that the first valid
byte of the cell is available to sample on the 16-bit Receive Data
Bus (URDATA[15:0]).
UXCLK
J26
I
IPD
Source clock for UTOPIA transmit driven by Master ATM
Controller.
UXCLAV
H27
O/Z
Transmit cell available status output signal from UTOPIA Slave.
IPD
0 indicates a complete cell is NOT available for transmit.
1 indicates a complete cell is available for transmit.
UXADDR0
W29
UXADDR1
W28
UXADDR2
W27
I
IPD
UTOPIA transmit address bus
UXADDR3
W26
UXADDR4
W25
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