TMS320C6472_16 Datasheet, PDF (160/269 Pages) Texas Instruments – TMS320C6472 Fixed-Point Digital Signal Processor

TMS320C6472
SPRS612G – JUNE 2009 – REVISED JULY 2011
7.8.4 PLL1 Controller Input and Output Clock Electrical Data/Timing
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(see Figure 7-23)
NO.
1
t_c(CLKIN1)
2
t_w(CLKIN1H)
3
t_w(CLKIN1L)
4
t_t(CLKIN1)
5
t_J(CLKIN1)
CLKIN1
Table 7-29. Timing Requirements for CLKIN1 Devices
Cycle time, CLKIN1
Pulse duration, CLKIN1 high
Pulse duration, CLKIN1 low
Transition time, CLKIN1
Period jitter (peak-to-peak), CLKIN1
5
1
2
500/625/700
PLL MODES
x10 to x32
MIN
MAX
20
80
0.4 * t_c(CLKIN1)
0.4 * t_c(CLKIN1)
1.2
100
UNIT
ns
ns
ns
ns
ps
4
3
4
Figure 7-23. CLKIN1 Timing
Table 7-30. Switching Characteristics Over Recommended Operating Conditions for
SYSCLKOUT [CPU/6]⁽¹⁾⁽²⁾
(see Figure 7-24)
500/625/700
NO.
PARAMETER
TYP
1
t_c(CLK)
Cycle time, SYSCLKOUT
6P
2
t_w(CLKH)
Pulse duration, SYSCLKOUT high
3P
3
t_w(CLKL)
Pulse duration, SYSCLKOUT low
3P
(1) The reference points for the rise and fall transitions are measured at 3.3 V V_OL MAX and V_OH MIN.
(2) P = 1/CPU clock frequency in nanoseconds (ns).
UNIT
ns
ns
ns
1
2
SYSCLKOUT
3
Figure 7-24. SYSCLKOUT Timing
160 C64x+ Peripheral Information and Electrical Specifications
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