TMS320C6472_16 Datasheet, PDF (237/269 Pages) Texas Instruments – TMS320C6472 Fixed-Point Digital Signal Processor

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TMS320C6472
SPRS612G – JUNE 2009 – REVISED JULY 2011
7.16 Timers
The timers can be used to: time events, count events, generate pulses, interrupt the CPU, and send
synchronization events to the EDMA. The localized timers (Timer 0 - Timer 5) can also be used as
watchdog timers.
7.16.1 Timer Device-Specific Information
The C6472 device has six localized timers (Timer 0 - Timer 5) and six shared timers (Timer 6 - Timer 11).
Each of the localized timers can be configured as a general-purpose timer or a watchdog timer. Each of
the shared timers is a general-purpose timer. When configured as a general-purpose timer, each timer
can be programmed as a 64-bit timer or as two separate 32-bit timers. The localized timers are clocked
with an internal clock with a CPU/6 frequency. The shared timers can also be clocked with the same
internal clock frequency or with an external signal provided on TIMI0 or TIMI1.
Each timer is made up of two 32-bit counters: a high counter and a low counter. The TIMI0 pin is
connected to the low counter of each of the shared timers and the TIMI1 pin is connected to the high
counter of each of the shared timers. The output of one of the shared timers, either the high counter or the
low counter, can be selected to be output on the timer output pin (TIMO2).
When Timer 0 - Timer 5 are configured as watchdog timers, each core should maintain its own watchdog.
Each core should also configure the corresponding RSTMUX0-5 register (see Section 3.8.2) to define the
action that will be taken if a watchdog timeout occurs. In addition to the internally defined actions, a
watchdog timeout results in the assertion of the WDOUT pin. WDOUT is a logically-combined signal from
the six individual watchdog timers. A host can determine which of the six cores experienced the watchdog
timeout by reading the RSTMUX registers or having the contents of those registers reported by one of the
cores.
7.16.2 Timer Peripheral Register Descriptions
HEX ADDRESS RANGE
025E 0000
025E 0004
025E 0008
025E 000C
025E 0010
025E 0014
025E 0018
025E 001C
025E 0020
025E 0024
025E 0028
025E 002C - 025E FFFC
Table 7-127. Timer 0 Registers
ACRONYM
-
EMUMGT_CLKSPD0
-
-
CNTLO0
CNTHI0
PRDLO0
PRDHI0
TCR0
TGCR0
WDTCR0
-
REGISTER NAME
Reserved
Timer 0 Emulation Management/Clock Speed Register
Reserved
Reserved
Timer 0 Counter Register Low
Timer 0 Counter Register High
Timer 0 Period Register Low
Timer 0 Period Register High
Timer 0 Control Register
Timer 0 Global Control Register
Timer 0 Watchdog Timer Control Register
Reserved
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C64x+ Peripheral Information and Electrical Specifications 237
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