TMS320C6472_16 Datasheet, PDF (201/269 Pages) Texas Instruments – TMS320C6472 Fixed-Point Digital Signal Processor

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HEX ADDRESS RANGE
0254 1120 - 0254 113C
0254 1140 - 0254 115C
0254 1160 - 0254 117C
0254 1180 - 0254 17FC
0254 1800 - 0254 181C
0254 1820 - 0254 183C
0254 1840 - 0254 185C
0254 1860 - 0254 187C
0254 1880 - 0254 189C
0254 18A0 - 0254 18BC
0254 18C0 - 0254 18DC
0254 18E0 - 0254 18FC
0254 1900 - 0254 191C
0254 1920 - 0254 193C
0254 1940 - 0254 195C
0254 1960 - 0254 197C
0254 1980 - 0254 19FC
TMS320C6472
SPRS612G – JUNE 2009 – REVISED JULY 2011
Table 7-79. DMATCU Channel Registers (continued)
ACRONYM
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
REGISTER NAME
Transmit Channel 4 Config B Registers
Transmit Channel 5 Config A Registers
Transmit Channel 5 Config B Registers
Reserved
Receive Channel 0 Config A Registers
Receive Channel 0 Config B Registers
Receive Channel 1 Config A Registers
Receive Channel 1 Config B Registers
Receive Channel 2 Config A Registers
Receive Channel 2 Config B Registers
Receive Channel 3 Config A Registers
Receive Channel 3 Config B Registers
Receive Channel 4 Config A Registers
Receive Channel 4 Config B Registers
Receive Channel 5 Config A Registers
Receive Channel 5 Config B Registers
Reserved
HEX ADDRESS RANGE
0254 1000
0254 1004
0254 1008
0254 100C
0254 1010 - 0254 101C
0254 1020
0254 1024
0254 1028
0254 102C
0254 1030 - 0254 103C
0254 1040
0254 1044
0254 1048
0254 104C
0254 1050 - 0254 105C
0254 1060
0254 1064
0254 1068
0254 106C
0254 1070 - 0254 107C
0254 1080
0254 1084
0254 1088
0254 108C
0254 1090 - 0254 109C
0254 10A0
0254 10A4
Table 7-80. DMATCU Transmit Channels 0-5 Registers
ACRONYM
DXCH_ABASE0
DXCH_AFALLOC0
DXCH_AFSIZE0
DXCH_AFCNT0
-
DXCH_BBASE0
DXCH_BFALLOC0
DXCH_BFSIZE0
DXCH_BFCNT0
-
DXCH_ABASE1
DXCH_AFALLOC1
DXCH_AFSIZE1
DXCH_AFCNT1
-
DXCH_BBASE1
DXCH_BFALLOC1
DXCH_BFSIZE1
DXCH_BFCNT1
-
DXCH_ABASE2
DXCH_AFALLOC2
DXCH_AFSIZE2
DXCH_AFCNT2
-
DXCH_BBASE2
DXCH_BFALLOC2
REGISTER NAME
Transmit Channel 0 Memory Base Address Register A
Transmit Channel 0 Frame Allocation Register A
Transmit Channel 0 Frame Size Register A
Transmit Channel 0 Frame Count Register A
Reserved
Transmit Channel 0 Memory Base Address Register B
Transmit Channel 0 Frame Allocation Register B
Transmit Channel 0 Frame Size Register B
Transmit Channel 0 Frame Count Register B
Reserved
Transmit Channel 1 Memory Base Address Register A
Transmit Channel 1 Frame Allocation Register A
Transmit Channel 1 Frame Size Register A
Transmit Channel 1 Frame Count Register A
Reserved
Transmit Channel 1 Memory Base Address Register B
Transmit Channel 1 Frame Allocation Register B
Transmit Channel 1 Frame Size Register B
Transmit Channel 1 Frame Count Register B
Reserved
Transmit Channel 2 Memory Base Address Register A
Transmit Channel 2 Frame Allocation Register A
Transmit Channel 2 Frame Size Register A
Transmit Channel 2 Frame Count Register A
Reserved
Transmit Channel 2 Memory Base Address Register B
Transmit Channel 2 Frame Allocation Register B
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C64x+ Peripheral Information and Electrical Specifications 201
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