TMS320C6472_16 Datasheet, PDF (156/269 Pages) Texas Instruments – TMS320C6472 Fixed-Point Digital Signal Processor

TMS320C6472
SPRS612G – JUNE 2009 – REVISED JULY 2011
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7.8.3.6 PLL1 PLL Controller Command Register (PLLCMD)
The PLL controller command register (PLLCMD) controls the SYSCLK rate change and phase alignment.
The PLLCMD register is shown in Figure 7-19 and described in Table 7-25.
31
Reserved
R-0
15
2
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-19. PLL Controller Command Register (PLLCMD)
16
1
Rsvd
R/W-0
0
GOSET
R/W-0
Table 7-25. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit Field
31:1 Reserved
0 GOSET
Value
0
0
1
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
GO operation command for SYSCLK rate change and phase alignment. Before setting this bit to 1
to initiate a GO operation, check the GOSTAT bit in the PLLSTAT register to ensure all previous
GO operations have completed.
No effect. Write of 0 clears bit to 0.
Initiates GO operation. Write of 1 initiates GO operation. Once set, GOSET remains set but further
writes of 1 can initiate the GO operation.
156 C64x+ Peripheral Information and Electrical Specifications
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