TMS320C6472_16 Datasheet, PDF (246/269 Pages) Texas Instruments – TMS320C6472 Fixed-Point Digital Signal Processor

TMS320C6472
SPRS612G – JUNE 2009 – REVISED JULY 2011
www.ti.com
Table 7-146. Timing Requirements for UTOPIA Slave Receive Cycles
(see Figure 7-63)
500/625/700
NO.
MIN
MAX
5
t_{su(URDATA−URCLKH)} Setup time, URDATA valid before URCLK high
4
6
t_{h(URCLKH−URDATA)}
Hold time, URDATA valid after URCLK high
1
7
t_{su(URADDR−URCLKH)} Setup time, URADDR valid before URCLK high
4
8
t_{h(URCLKH−URADDR)}
Hold time, URADDR valid after URCLK high
1
9
t_{su(URENB−URCLKH)}
Setup time, URENB valid before URCLK high
4
10
t_{h(URCLKH−URENB)}
Hold time, URENB valid after URCLK high
1
11
t_{su(URSOC−URCLKH)}
Setup time, URSOC valid before URCLK high
4
12
t_{h(URCLKH−URSOC)}
Hold time, URSOC valid after URCLK high
1
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
Table 7-147. Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave
Receive Cycles
(see Figure 7-63)
NO.
13 ⁽¹⁾
14 ⁽¹⁾
15 ^{(2) (3)}
t_{d(URCLKH−URCLAV)}
t_{en(URCLKH−URCLAV)}
t_{dis(URCLKL−URCLAVZ)}
PARAMETER
Delay time, URCLK high to URCLAV valid
Enable time, URCLK high to URCLAV driven
Disable time, URCLK low to URCLAV high-impedance state
500/625/700
MIN MAX
2
10
2
10
2
10
UNIT
ns
ns
ns
(1) MAX delay time and enable time increases to 12.5 ns at 20 pF and 14 ns at 30 pF, specified by design.
(2) Specifed by design for MIN values.
(3) Specifed by design for MAX values.
URCLK
(input)
5
URDATA[15:0]
P48
(input)
URADDR[4:0] _N
1Fh
(input)
6
7
N+1
URCLAV
(output)
URENB
(input)
URSOC
(input)
N
10
H1
8
1Fh
14 13
N+1
9
11
H2
H3
N+2
1Fh
15
N+2
12
Figure 7-63. UTOPIA Slave Receive
246 C64x+ Peripheral Information and Electrical Specifications
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