TMS320C6472_16 Datasheet, PDF (195/269 Pages) Texas Instruments – TMS320C6472 Fixed-Point Digital Signal Processor

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TMS320C6472
SPRS612G – JUNE 2009 – REVISED JULY 2011
Table 7-66. DMATCU Transmit Channels 0-5 Registers (continued)
HEX ADDRESS RANGE
0250 116C
0250 1170 - 0250 117C
ACRONYM
DXCH_BFCNT5
-
REGISTER NAME
Transmit Channel 5 Frame Count Register B
Reserved
HEX ADDRESS RANGE
0250 1800
0250 1804
0250 1808
0250 180C
0250 1810 - 0250 181C
0250 1820
0250 1824
0250 1828
0250 182C
0250 1830 - 0250 183C
0250 1840
0250 1844
0250 1848
0250 184C
0250 1850 - 0250 185C
0250 1860
0250 1864
0250 1868
0250 186C
0250 1870 - 0250 187C
0250 1880
0250 1884
0250 1888
0250 188C
0250 1890 - 0250 189C
0250 18A0
0250 18A4
0250 18A8
0250 18AC
0250 18B0 - 0250 18BC
0250 18C0
0250 18C4
0250 18C8
0250 18CC
0250 18D0 - 0250 18DC
0250 18E0
0250 18E4
0250 18E8
0250 18EC
0250 18F0 - 0250 18FC
0250 1900
0250 1904
Table 7-67. DMATCU Receive Channels 0-5 Registers
ACRONYM
DRCH_ABASE0
DRCH_AFALLOC0
DRCH_AFSIZE0
DRCH_AFCNT0
-
DRCH_BBASE0
DRCH_BFALLOC0
DRCH _BFSIZE0
DRCH _BFCNT0
-
DRCH_ABASE1
DRCH_AFALLOC1
DRCH_AFSIZE1
DRCH_AFCNT1
-
DRCH_BBASE1
DRCH_BFALLOC1
DRCH _BFSIZE1
DRCH _BFCNT1
-
DRCH_ABASE2
DRCH_AFALLOC2
DRCH_AFSIZE2
DRCH_AFCNT2
-
DRCH_BBASE2
DRCH_BFALLOC2
DRCH _BFSIZE2
DRCH _BFCNT2
-
DRCH_ABASE3
DRCH_AFALLOC3
DRCH_AFSIZE3
DRCH_AFCNT3
-
DRCH_BBASE3
DRCH_BFALLOC3
DRCH _BFSIZE3
DRCH _BFCNT3
-
DRCH_ABASE4
DRCH_AFALLOC4
REGISTER NAME
Receive Channel 0 Memory Base Address Register A
Receive Channel 0 Frame Allocation Register A
Receive Channel 0 Frame Size Register A
Receive Channel 0 Frame Count Register A
Reserved
Receive Channel 0 Memory Base Address Register B
Receive Channel 0 Frame Allocation Register B
Receive Channel 0 Frame Size Register B
Receive Channel 0 Frame Count Register B
Reserved
Receive Channel 1 Memory Base Address Register A
Receive Channel 1 Frame Allocation Register A
Receive Channel 1 Frame Size Register A
Receive Channel 1 Frame Count Register A
Reserved
Receive Channel 1 Memory Base Address Register B
Receive Channel 1 Frame Allocation Register B
Receive Channel 1 Frame Size Register B
Receive Channel 1 Frame Count Register B
Reserved
Receive Channel 2 Memory Base Address Register A
Receive Channel 2 Frame Allocation Register A
Receive Channel 2 Frame Size Register A
Receive Channel 2 Frame Count Register A
Reserved
Receive Channel 2 Memory Base Address Register B
Receive Channel 2 Frame Allocation Register B
Receive Channel 2 Frame Size Register B
Receive Channel 2 Frame Count Register B
Reserved
Receive Channel 3 Memory Base Address Register A
Receive Channel 3 Frame Allocation Register A
Receive Channel 3 Frame Size Register A
Receive Channel 3 Frame Count Register A
Reserved
Receive Channel 3 Memory Base Address Register B
Receive Channel 3 Frame Allocation Register B
Receive Channel 3 Frame Size Register B
Receive Channel 3 Frame Count Register B
Reserved
Receive Channel 4 Memory Base Address Register A
Receive Channel 4 Frame Allocation Register A
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C64x+ Peripheral Information and Electrical Specifications 195
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