DS90CR286AT-Q1 Datasheet, PDF (3/29 Pages) Texas Instruments – Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link 66 MHz

www.ti.com
5 Pin Configuration and Functions
DGG Package
56-Pin TSSOP
Top View
DS90CR286AT-Q1
SNLS498A – NOVEMBER 2015 – REVISED DECEMBER 2015
PIN
NAME
NO.
RxIN0+, RxIN0-,
RxIN1+, RxIN1-,
RxIN2+, RxIN2-,
RxIN3+, RxIN3-
10, 9,
12, 11,
16, 15,
20, 19
RxCLKIN+,
18,
RxCLKIN-
17
RxOUT[27:0]
RxCLK OUT
PWR DWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
7, 6, 5, 3,
2, 1, 55, 54,
53, 51, 50, 49,
47, 46, 45, 43,
42, 41, 39, 38,
37, 35, 34, 33,
32, 30, 29, 27
26
25
56, 48, 40, 31
52, 44, 36,
28, 4
23
24, 22
13
21, 14, 8
I/O , TYPE
I, LVDS
I, LVDS
Pin Functions
PIN DESCRIPTION
Positive and negative LVDS differential data inputs. 100 Ω termination resistors
should be placed between RxIN+ and RxIN- receiver inputs as close as
possible to the receiver pins for proper signaling.
Positive and negative LVDS differential clock input. 100 Ω termination resistor
should be placed between RxCLKIN+ and RxCLKIN- receiver inputs as close
as possible to the receiver pins for proper signaling.
O, LVCMOS LVCMOS level data outputs.
O, LVCMOS
I, LVCMOS
Power
Power
Power
Power
Power
Power
LVCMOS Ievel clock output. The rising edge acts as the data strobe.
LVCMOS level input. When asserted low, the receiver outputs are low.
Power supply pins for LVCMOS outputs.
Ground pins for LVCMOS outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: DS90CR286AT-Q1
Submit Documentation Feedback
3