DS90CR286AT-Q1 Datasheet, PDF (14/29 Pages) Texas Instruments – Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link 66 MHz

DS90CR286AT-Q1
SNLS498A – NOVEMBER 2015 – REVISED DECEMBER 2015
8 Application and Implementation
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NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DS90CR286AT-Q1 is designed for a wide variety of data transmission applications. The use of serialized
LVDS data lines in these applications allows for efficient signal transmission over a narrow bus width, thereby
reducing cost, power, and space. The DS90CR286AT-Q1 is designed for PCB board chip-to-chip OpenLDI-to-
RGB (LVDS-to-parallel) bridge conversion. LVDS data transmission over cable interconnect is not recommended
for this device. Users designing a sub-system with a compatible OpenLDI transmitter and DS90CR286AT-Q1
receiver must ensure an acceptable skew margin budget (RSKM).
8.2 Typical Application
PCB Trace
DS90CR286AT-Q1 28-Bit Rx
LVDS Data
RxOUT[27:0]
24-Bit RGB Display Unit
Graphics Processor Unit (GPU)
28-Bit Tx Data
(4 LVDS Data, 1 LVDS Clock)
LVDS Clock
RxCLK
PLL
Figure 22. Typical DS90CR286AT-Q1 Application Block Diagram
8.2.1 Design Requirements
For this design example, ensure that the following requirements are observed.
Table 1. DS90CR286AT-Q1 Design Parameters
DESIGN PARAMETER
Operating Frequency
Bit Resolution
Bit Data Mapping
RSKM (Receiver Skew Margin)
Input Termination for RxIN±
RxIN± Board Trace Impedance
LVCMOS Outputs
DC Power Supply Coupling Capacitors
DESIGN REQUIREMENTS
LVDS clock must be within 20-66 MHz.
No higher than 24 bpp. The maximum supported resolution is 8-bit RGB.
Determine the appropriate mapping required by the panel display following the
DS90CR286AT-Q1 outputs.
Ensure that there is acceptable margin between Tx pulse position and Rx
strobe position.
100 Ω ± 10% resistor across each LVDS differential pair. Place as close as
possible to IC input pins.
Design differential trace impedance with 100 Ω ± 5%.
If unused, leave pins floating. Series resistance on each LVCMOS output
optional to reduce reflections from long board traces. If used, 33 Ω series
resistance is typical.
Use a 0.1 µF capacitor to minimize power supply noise. Place as close as
possible to Vcc pins.
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