DS90CR286AT-Q1 Datasheet, PDF (15/29 Pages) Texas Instruments – Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link 66 MHz

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DS90CR286AT-Q1
SNLS498A – NOVEMBER 2015 – REVISED DECEMBER 2015
8.2.2 Detailed Design Procedure
To begin the design process with the DS90CR286AT-Q1, determine the following:
• Operating Frequency
• Bit Resolution of the Panel
• Bit Mapping from Receiver to Endpoint Panel Display
• RSKM Interoperability with Transmitter Pulse Position Margin
8.2.2.1 Bit Resolution and Operating Frequency Compatibility
The bit resolution of the endpoint panel display reveals whether there are enough bits available in the
DS90CR286AT-Q1 to output the required data per pixel. The DS90CR286AT-Q1 has 28 parallel LVCMOS
outputs and can therefore provide a bit resolution up to 24 bpp (bits per pixel). In each clock cycle, the remaining
bits are the three control signals (HSync, VSync, DE) and one spare bit.
The number of pixels per frame and the refresh rate of the endpoint panel display indicate the required operating
frequency of the receiver clock. To determine the required clock frequency, refer to the following formula:
f_Clk = [H_Active + H_Blank] × [V_Active + V_Blank] × f_Vertical
where
• H_Active = Active Display Horizontal Lines
• H_Blank = Blanking Period Horizontal Lines
• V_Active = Active Display Vertical Lines
• V_Blank = Blanking Period Vertical Lines
• f_Vertical = Refresh Rate (in Hz)
• f_Clk = Operating Frequency of LVDS clock
(1)
In each frame, there is a blanking period associated with horizontal rows and vertical columns that are not
actively displayed on the panel. These blanking period pixels must be included to determine the required clock
frequency. Consider the following example to determine the required LVDS clock frequency:
• H_Active = 640
• H_Blank = 40
• V_Active = 480
• V_Blank = 41
• f_Vertical = 59.95 Hz
Thus, the required operating frequency is determined below:
[640 + 40] x [480 + 41] x 59.95 = 21239086 Hz ≈ 21.24 MHz
(2)
Since the operating frequency for the PLL in the DS90CR286AT-Q1 ranges from 20-66 MHz, the
DS90CR286AT-Q1 can support a panel display with the aforementioned requirements.
If the specific blanking interval is unknown, the number of pixels in the blanking interval can be approximated to
20% of the active pixels. The following formula can be used as a conservative approximation for the operating
LVDS clock frequency:
f_Clk ≈ H_Active x V_Active x f_Vertical x 1.2
(3)
Using this approximation, the operating frequency for the example in this section is estimated below:
640 x 480 x 59.95 x 1.2 = 22099968 Hz ≈ 22.10 MHz
(4)
8.2.2.2 Data Mapping between Receiver and Endpoint Panel Display
Ensure that the LVCMOS outputs are mapped to align with the endpoint display RGB mapping requirements
following the deserializer. Two popular mapping topologies for 8-bit RGB data are shown below:
1. LSBs are mapped to RxIN3±.
2. MSBs are mapped to RxIN3±.
The following tables depict how these two popular topologies can be mapped to the DS90CR286AT-Q1 outputs.
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