DS90CR286AT-Q1 Datasheet, PDF (18/29 Pages) Texas Instruments – Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link 66 MHz

DS90CR286AT-Q1
SNLS498A – NOVEMBER 2015 – REVISED DECEMBER 2015
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If there is less left bit margin than right bit margin, the LVDS clock can be delayed so that the Rx strobe position
for incoming data appears to be delayed. If there is less right bit margin than left bit margin, all the LVDS data
pairs can be delayed uniformly so that the LVDS clock and Rx strobe position for incoming data appear to
advance. To delay an LVDS data or clock pair, designers can either add more PCB trace length or install a
capacitor between the LVDS transmitter and receiver. It is important to note that when using these techniques, all
serialized bit positions are shifted right or left uniformly.
When designing the DS90CR286AT-Q1 receiver with a third-party OpenLDI transmitter, users must calculate the
skew margin budget (RSKM) based on the Tx pulse position and the Rx strobe position to ensure error-free
transmission. For more information about calculating RSKM, refer to Application Note SNLA249.
8.2.3 Application Curves
The following application curves are examples taken with a DS90C385 serializer interfacing to a DS90CR286AT-
Q1 deserializer in nominal temperature (25ºC) at an operating frequency of 66 MHz.
TxIN7 TxIN6 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0
Time (2.5 ns/DIV)
Figure 24. LVDS RxIN0± aligned with LVCMOS RxCLKOUT
Time (5.0 ns/DIV)
Figure 25. LVDS CLKIN aligned with LVCMOS RxCLKOUT
Time (5.0 ns/DIV)
Figure 26. RxOUT and RxCLKOUT Timing Diagram
Time (20.0 ns/DIV)
Figure 27. PRBS-7 Output on RxOUT Channels
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