DS90CR286AT-Q1 Datasheet, PDF (17/29 Pages) Texas Instruments – Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link 66 MHz

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DS90CR286AT-Q1
SNLS498A – NOVEMBER 2015 – REVISED DECEMBER 2015
LVDS INPUT
CHANNEL
RxIN2
RxIN3
Table 3. 8-Bit Color Mapping with MSBs on RxIN3± (continued)
LVDS BIT STREAM
POSITION
TxIN19
TxIN20
TxIN21
TxIN22
TxIN24
TxIN25
TxIN26
TxIN27
TxIN5
TxIN10
TxIN11
TxIN16
TxIN17
TxIN23
LVCMOS OUTPUT
CHANNEL
RxOUT19
RxOUT20
RxOUT21
RxOUT22
RxOUT24
RxOUT25
RxOUT26
RxOUT27
RxOUT5
RxOUT10
RxOUT11
RxOUT16
RxOUT17
RxOUT23
COLOR MAPPING
B2
B3
B4
B5
HSYNC
VSYNC
DE
R6
R7
G6
G7
B6
B7
GP
COMMENTS
Horizontal Sync
Vertical Sync
Data Enable
MSB
MSB
MSB
General Purpose
In situations where the DS90CR286AT-Q1 must support 18 bpp, Table 2 is commonly used. With this mapping,
MSBs of RGB data are retained on RXIN0±, RXIN1±, and RXIN2± while the two LSBs for the original 8-bit RGB
resolution are ignored from RxIN3±.
8.2.2.3 RSKM Interoperability
One of the most important factors when designing the receiver into a system application is assessing how much
RSKM (Receiver Skew Margin) is available. In each LVDS clock cycle, the LVDS data stream carries seven
serialized data bits. Ideally, the Transmit Pulse Position for each bit will occur every (n x T)/7 seconds, where n =
Bit Position and T = LVDS Clock Period. Likewise, ideally the Receive Strobe Position for each bit will occur
every ((n + 0.5) x T)/7 seconds. However, due to the effects of clock jitter and ISI, both LVDS transmitter and
receiver in real systems will have a minimum and maximum pulse and strobe position, respectively, for each bit
position. This concept is illustrated in Figure 23:
Rspos0
min
max
Rspos1
min
max
Tppos0 Bit 0 Left Margin
min
max
Ideal Rx Strobe
Bit 0 Right Margin Tppos1 Bit 1 Left Margin
min
max
Position
Bit0
Bit 1 Right Margin Tppos2
Ideal Rx Strobe
min
max
Position
Bit1
Figure 23. RSKM Measurement Example
All left and right margins for Bits 0-6 must be considered in order to determine the absolute minimum for the
whole LVDS bit stream. This absolute minimum corresponds to the RSKM.
To improve RSKM performance between LVDS transmitter and receiver, designers may either advance or delay
the LVDS clock compared to the LVDS data. Moving the LVDS clock compared to the LVDS data can improve
the Rx strobe position compared to the Tx pulse position of the transmitter.
Copyright © 2015, Texas Instruments Incorporated
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