DS90CR286AT-Q1 Datasheet, PDF (12/29 Pages) Texas Instruments – Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link 66 MHz

DS90CR286AT-Q1
SNLS498A – NOVEMBER 2015 – REVISED DECEMBER 2015
7 Detailed Description
www.ti.com
7.1 Overview
The DS90CR286AT-Q1 is an AEC-Q100 Grade 2 receiver that converts four LVDS (Low Voltage Differential
Signaling) data streams back into parallel 28 bits of LVCMOS data (24 bits of RGB and 4 bits of HSYNC,
VSYNC, DE, and CNTL). An internal PLL locks to the incoming LVDS clock ranging from 20 to 66 MHz. The
locked PLL then ensures a stable clock to sample the output LVCMOS data on the Receiver Clock Out rising
edge. The DS90CR286AT-Q1 features a PWR DWN pin to put the device into low power mode when there is no
active input data.
7.2 Functional Block Diagram
4 x LVDS Data
(140 to 462 Mbps on
Each LVDS Channel)
28 x LVCMOS
Outputs
LVDS Clock
PLL
(20 to 66 MHz)
Figure 20. DS90CR286AT-Q1 Block Diagram
Receiver Clock Out
PWR DWN
7.3 Feature Description
The DS90CR286AT-Q1 consists of several key blocks:
• LVDS Receivers
• Phase Locked Loop (PLL)
• Serial LVDS-to-Parallel LVCMOS Converter
• LVCMOS Drivers
7.3.1 LVDS Receivers
There are five differential LVDS inputs to the DS90CR286AT-Q1. Four of the LVDS inputs contain serialized data
originating from a 28-bit source transmitter. The remaining LVDS input contains the LVDS clock associated with
the data pairs.
12
Submit Documentation Feedback
Product Folder Links: DS90CR286AT-Q1
Copyright © 2015, Texas Instruments Incorporated