DRV8850_16 Datasheet, PDF (3/30 Pages) Texas Instruments – Low-Voltage H-Bridge IC with LDO Voltage Regulator

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5 Pin Configuration and Functions
RGY Package
24-Pin VQFN
Top View
DRV8850
SLVSCC0B – NOVEMBER 2013 – REVISED DECEMBER 2015
OUT1 ²
OUT1 3
OUT1 4
IN1H 5
IN1L ⁶
IN2H 7
IN2L 8
nSLEEP ⁹
LDOEN ¹⁰
SR ¹¹
GND
(The1rmal
Pad)
23 OUT2
22 OUT2
21 _OUT2
20 _VCC
19 _VCC
18 _VCC
17 _VCP
16 VPROPI
15 _LDOOUT
14 LDOFB
PIN
NAME
NO.
POWER AND GROUND
GND
1, 12, 13, 24,
Thermal pad
LDOOUT
15
VCC
21, 22, 23
VCP
17
CONTROL
IN1H
5
IN1L
6
IN2H
7
IN2L
8
LDOEN
10
LDOFB
14
nSLEEP
9
SR
11
I/O ⁽¹⁾
Pin Functions
DESCRIPTION
EXTERNAL COMPONENTS OR CONNECTIONS
—
Device ground
—
LDO regulator output
—
Device supply
—
Charge pump
Bypass to GND with a 2.2-μF 6.3-V ceramic capacitor
Bypass to GND with 0.1-μF and 10-μF 6.3-V ceramic capacitors
Connect a 0.1-μF 6.3-V ceramic capacitor to VCC
I
Input 1 HS FET enable
Active high enables HS FET for output 1
Internal pulldown resistor
I
Input 1 LS FET enable
Active high enables LS FET for output 1
Internal pulldown resistor
I
Input 2 HS FET enable
Active high enables HS FET for output 2
Internal pulldown resistor
I
Input 2 LS FET enable
Active high enables LS FET for output 2
Internal pulldown resistor
Logic low disables LDO regulator
I
LDO regulator enable
Logic high enables LDO regulator
Internal pulldown resistor
I
LDO regulator feedback
Resistor divider from LDOOUT sets LDO output voltage
May be connected to LDOIN to enable LDO
I
Sleep mode input
Logic low puts device in low-power sleep mode
Logic high for typical operation
Internal pulldown resistor
IO
Slew rate control
Resistor to ground sets output slew rate
(1) Directions: I = input, O = output, OZ = 3-state output, OD = open-drain output, IO = input or output
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