DRV8850_16 Datasheet, PDF (13/30 Pages) Texas Instruments – Low-Voltage H-Bridge IC with LDO Voltage Regulator

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DRV8850
SLVSCC0B – NOVEMBER 2013 – REVISED DECEMBER 2015
Feature Description (continued)
Table 2 lists the operation mode logic for the DRV8850 device.
Table 2. DRV8850 Device Operation Mode Logic⁽¹⁾
nSLEEP
0
0
1
1
LDOEN
0
1
0
1
LDO
REGULATOR
Off
Active
Off
Active
DRIVER
Sleep
Sleep
Active
Active
(1) A state must be active for a minimum of 1 ms before a new state is
commanded.
7.3.2 Bridge Control
A corresponding input pin controls the individual FETs in the DRV8850 device. Shoot-through (the condition
when both HS and LS FETs are turned on at the same time) is not allowed; with this input condition, both the HS
and LS FETs turn off.
Table 3 lists the logic for the DRV8850 device.
Table 3. DRV8850 Device Logic
INxL
0
0
1
1
INxH
0
1
0
1
OUTx
Z
H
L
Z
7.3.3 Current Sensing – VPROPI
The VPROPI pin outputs an analog current that is proportional to the current flowing in the H-bridge. The output
current is typically 1 / 2000 of the current in both high side FETs. VPROPI is derived from the current through
either of the high side FETs. Because of this, VPROPI does not represent the H-bridge current when operating in
a fast-decay mode or low-side slow-decay mode. VPROPI represents the H-bridge current under forward drive,
reverse drive, and high-side slow decay. VPROPI output is delayed by roughly 2 µs after the high side FET is
switched on and it has reached approximately VCC (including the deglitch on the HSon). Select the external
resistor so that the voltage on VPROPI is less than (VCC – 1 V), so the resistor must be sized less than:
2000 x VCC 1 V / IOUT
(1)
where I_OUT is the maximum drive current to be monitored
The range of current that can be monitored is 500 mA to 5 A, assuming the external resistor meets Equation 1.
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