DRV8850_16 Datasheet, PDF (15/30 Pages) Texas Instruments – Low-Voltage H-Bridge IC with LDO Voltage Regulator

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DRV8850
SLVSCC0B – NOVEMBER 2013 – REVISED DECEMBER 2015
7.3.4 Slew-Rate Control
The rise and fall times (t_R and t_F) of the outputs can be adjusted by the value of an external resistor connected
from the SR pin to ground. The output slew rate is adjusted internally by the DRV8850 device by controlling the
ramp rate of the driven FET gate.
The typical voltage on the SR pin is 0.6 V driven internally. Changing the resistor value monotonically increases
the slew rates from approximately 100 ns to 100 µs. Recommended values for the external resistor are from
GND to 2.4 MΩ. If the SR pin is grounded then the slew rate is 100 ns.
7.3.5 Dead Time
The dead time (t_DEAD) is measured as the time when OUTx is Hi-Z between turning off one of the H-bridge FETs
and turning on the other. For example, the output is Hi-Z between turning off the high-side FET and turning on
the low-side FET. When driving current out of the pin, the output is observed to fall to one diode drop below
ground during dead time. When driving current into the pin, the output is observed to rise to one diode drop
above VCC.
The DRV8850 has an analog dead time of approximately 100 ns. In addition to this analog dead time, the output
is Hi-Z when the FET gate voltage is less than the threshold voltage. The total dead time depends on the SR
resistor setting because a portion of the FET gate ramp includes the observable dead time.
7.3.6 Propagation Delay
The propagation delay time (t_DELAY) is measured as the time between an input edge to an output change. This
time is composed of two parts: an input deglitcher and output slewing delay. The input deglitcher prevents noise
on the input pins from affecting the output state.
The output slew rate also contributes to the delay time. For the output to change state during typical operation,
first one FET must be turned off. The FET gate is ramped down according to the SR resistor selection, and the
observed propagation delay ends when the FET gate falls to less than the threshold voltage.
INxH
INxL
High-side
Gate
HS Slew Rate
HS Slew Rate
Low-side
Gate
LS Slew Rate
LS Slew Rate
OUTx
t_DELAY
t_DEAD
t_R
t_DELAY
t_F
t_DEAD
Figure 16. Low-Side Slow Decay Operation – Current Sourced from OUTx
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