TLC34075-135FN Datasheet, PDF (28/52 Pages) Texas Instruments – Video Interface Palette Data Manual

During special nibble mode, the input mux circuit latches all 8-bit inputs but only passes on the specified
nibble. The specified nibble is stored in the 4 LSBs of the next register pipe after the input latch, and the
4 MSBs are zeroed in that register. The register pipe contents are then passed to the read mask block. With
this structure, the palette page register still functions normally, providing good flexibility to users.
If the general control register bit 3 = 0 and bit 2 = 0, both split shift register transfers and special nibble mode
are disabled and the SFLAG/NFLAG input is ignored.
VCLK
BLANK
(at its input pin) _†
SFLAG/NFLAG _Valid
Input
LOAD
‡
Don’t Care
Latch Last Group
of Pixel Data
Valid
Latch First Group
of Pixel Data
Sampled
BLANK
PIXEL DATA
Last Group of Pixel Data
2nd
4th
1st Group 3rd _Group 5th
Group
Group
Group
SCLK
† _CAUTION:
If the data is not held valid until SCLK and BLANK both go low, the last few pixels could be missed.
‡ _{Setup time to next VCLK falling edge after BLANK high (must be met, otherwise the first pixel data}
could be missed).
Figure 12. SFLAG/NFLAG Timing in Special Nibble Mode
2.10 MUXOUT Output
MUXOUT is a TTL-compatible output. It is software programmable and is used to control external devices.
Its typical application is to select the HSYNC and VSYNC inputs between the VGA pass-through mode and
the normal modes (see Section 2.8). This output is driven low at power-up or when VGA pass-through mode
is selected; at any other time it can be programmed to the desired polarity via general control register bit
7.
2.11 General Control Register
The general control register is used to control HSYNC and VSYNC polarity, split shift register transfer
enabling, special nibble mode, sync control, the ones accumulation clock source, and the VGA
pass-through indicator. The bit field definitions are as follows:
2–16