TLC34075-135FN Datasheet, PDF (20/52 Pages) Texas Instruments – Video Interface Palette Data Manual

2.4.2 Multiplexing Modes
In addition to the VGA pass-through mode, there are four multiplexing modes available, all of which are
referred to as normal modes. In each normal mode, a pixel bus width of 8, 16, or 32 bits may be used. Modes
1, 2, and 3 also support a pixel bus width of 4 bits. Data should always be presented on the least significant
bits of the pixel bus. For example, when a 16-bit-wide pixel bus is used and there are 8 bits per pixel, each
8-bit pixel should be presented on P<0:7>. All the unused pixel bus pins should be connected to GND.
Mode 1 uses a single bit plane to address the color palette. The pixel port bit is fed into bit 0 of the palette
address, with the 7 high-order address bits being defined by the palette page register (see Section 2.2.3).
This mode has uses in high-resolution monochrome applications such as desktop publishing. This mode
allows the maximum amount of multiplexing (a 32:1 ratio), thus giving a pixel bus rate of only 4 MHz at a
screen resolution of 1280 by 1024. Although only a single bit plane is used, alteration of the palette page
register at the line frequency allows 256 different colors to be displayed simultaneously with 2 colors per
line.
Mode 2 uses 2 bit planes to address the color palette. The 2 bits are fed into the low-order address bits of
the palette with the 6 high-order address bits being defined by the palette page register (see Section 2.2.3).
This mode allows a maximum divide ratio of 16:1 on the pixel bus and is a 4-color alternative to mode 1.
Mode 3 uses 4 bit planes to address the color palette. The 4 bits are fed into the low-order address bits of
the palette with the 4 high-order address bits being defined by the palette page register (see Section 2.2.3).
This mode provides 16 pages of 16 colors and can be used at SCLK divide ratios of 1 to 8.
Mode 4 uses 8 bit planes to address the color palette. Since all 8 bits of palette address are specified from
the pixel port, the page register is not used. This mode allows dot-clock-to-SCLK ratios of 1:1 (8-bit bus),
2:1 (16-bit bus) or 4:1 (32-bit bus). Therefore, in a 32-bit configuration, a 1024-by-768 pixel screen can be
implemented with an external data rate of only 16 MHz.
2.4.3 True Color Mode
Mode 5 is true color mode, in which 24 bits of data are transferred from the pixel port directly to the DACs
with the same amount of pipeline delay as the overlay data and the control signals (BLANK and SYNCs).
In this mode, overlay is provided by using the remaining 8 bits of the pixel bus to address the palette RAM,
resulting in a 24-bit RAM output that is then used as overlay information to the DACs. When all the overlay
inputs (P<0:7>) are at a low logic level or the pixel read mask register is loaded with the value 0, no overlay
information is displayed; when a nonzero value is input with the pixel read mask enabled, the color palette
RAM is addressed and the resulting data is then fed through to the DACs, receiving priority over the true
color data.
The true-color-mode data input only works in the 8-bit mode. In other words, if only 6 bits are used, the 2
MSB inputs for each color should be tied to GND. However, the palette, which is used by the overlay input,
is still governed by the 8/6 input pin, and the output MUX selects 8 bits of data or 6 bits of data accordingly.
In the true color mode, P<15:8> pass red data, P<23:16> pass green data, and P<31:24> pass blue data.
2.4.4 Special Nibble Mode
Mode 6 is special nibble mode, which is enabled when the general control register SNM bit (bit 3) is set to
1 and the general control register SSRT bit (bit 2) is set to 0 (see Section 2.11). When special nibble mode
is enabled, it takes precedence over the other modes, and the mux control register setup is ignored. The
SFLAG/NFLAG input is then used as a nibble flag to indicate which nibble of each byte holds the pixel data.
Special nibble mode is a variation of the 4-bit pixel mode with a 16-bit pixel width. All 32 inputs (P0 through
P31) are connected as 4 bytes, but the 16-bit data bus is composed of either the lower or upper nibble of
each of the 4 bytes. For more detailed information, refer to Section 2.9.2. Since this mode uses 4 bit planes
for each pixel, they are fed into the low-order address bits of the palette, with the 4 high-order address bits
being defined by the palette page register (see Section 2.2.3).
2.4.5 Multiplex Control Register
The multiplexer is controlled via the 8-bit multiplex control register. The bit fields of the register are in Table 6.
2–8