TLC34075-135FN Datasheet, PDF (18/52 Pages) Texas Instruments – Video Interface Palette Data Manual

VCLK
BLANK
at Input Pin
SFLAG/NFLAG
LOAD
(Internal Signal
for Data Latch)
BLANK
(Internal Signal
Before DOTCLK
Pipeline Delay)
PIXEL DATA
at Input Pin
SCLK
Latch Last Group
of Pixel Data
Latch First Group
of Pixel Data
Latch Last Group
of Pixel Data
Last
Group
3rd
5th
2nd _Group 4th _Group
Group
Group
1st Group of Pixel Data
6th
Group
SCLK Between Split Shift Register Transfer
and Regular Shift Register Transfer
NOTE:The SSRT function is enabled (general control register bit 2 = 1).
Figure 5. SCLK/VCLK Control Timing (SSRT Enabled,
SCLK Frequency = VCLK Frequency)
VCLK
BLANK
at Input Pin
LOAD
(Internal Signal
for Data Latch)
BLANK
(Internal Signal
Before DOTCLK
Pipeline Delay)
PIXEL DATA
at Input Pin
Latch Last Group
of Pixel Data
Latch First Group
of Pixel Data
Last Group of Pixel Data
G1rsotupG2rnodupG3rrodupG4rtohup G5rtohupG6rtohup
SCLK
Figure 6. SCLK/VCLK Control Timing (SSRT Disabled,
SCLK Frequency = 4 × VCLK Frequency)
2–6