TLC34075-135FN Datasheet, PDF (17/52 Pages) Texas Instruments – Video Interface Palette Data Manual

The falling edge of VCLK is used internally by the TLC34075 to sample and latch the BLANK input level.
When BLANK goes low, SCLK is disabled as soon as possible. In other words, if the last SCLK pulse is at
the high level while the sampled BLANK is low, SCLK is allowed to finish its cycle to low level, then SCLK
is held low until the sampled BLANK goes back high to enable it again. The VRAM shift register should be
updated during the BLANK active period, and the first SCLK pulse is used to clock the first valid pixel data
from the VRAM. The internal pipeline delay of the BLANK input is designed to be in phase with data at the
DAC output to the monitors. The logic described above works in situations wherein the SCLK period is
shorter than, equal to, or longer than the VCLK period.
Figure 5 shows the case wherein the SSRT (split shift register transfer) function is enabled. One SCLK pulse
with a minimum width of 15 ns is generated from the rising edge at the SFLAG input with specified delay.
This is designed to meet the VRAM timing requirement, and this SCLK pulse replaces the first SCLK in the
regular shift register transfer case as described above. Refer to Section 2.9 for the detailed explanation of
the SSRT function.
The SCLK output waveform may vary at the time that the sampled BLANK input is low. Refer to Appendix C
for details.
2.3.2 VCLK
The VCLK frequency can be selected to be 1/1, 1/2, 1/4, 1/8, 1/16, or 1/32 of that of the dot clock, or it can
be held at a high logic level. The default condition is for VCLK to be held at a high logic level. VCLK is not
used in VGA pass-through mode.
VCLK is used by a GSP or custom-designed control logic to generate control signals (BLANK, HSYNC, and
VSYNC). As can be seen from Figures 4, 5, 6, and 7, since the control signals are sampled by VCLK, it is
obvious that VCLK has to be enabled.
VCLK
BLANK
at Input Pin
LOAD
(Internal Signal
for Data Latch)
BLANK
(Internal Signal
Before DOTCLK
Pipeline Delay)
PIXEL DATA
at Input Pin
SCLK
Latch Last Group
of Pixel Data
Latch First Group
of Pixel Data
Latch Last Group
of Pixel Data
Last Group of Pixel Data
1st
Group
G2rnodupG3rrodupG4rtohupG5rtohup
6th
Group
NOTE: Either the SSRT function is disabled (general control register bit 2 = 0), or the SFLAG/NFLAG input is held low
if the SSRT function is enabled (general control register bit 2 = 1).
Figure 4. SCLK/VCLK Control Timing (SSRT Disabled,
SCLK Frequency = VCLK Frequency)
2–5