TLC34075-135FN Datasheet, PDF (13/52 Pages) Texas Instruments – Video Interface Palette Data Manual

2 Detailed Description
2.1 MPU Interface
The processor interface is controlled via read and write strobes (RD, WR), four register select pins
(RS<0:3>), and the 8/6 select pin. The 8/6 select pin is used to select between 8- or 6-bit operation and is
provided in order to maintain compatibility with the IMSG176/8 color palette. This operation is carried out
in order to utilize the maximum range of the DACs.
The internal register map is shown in Table 1. The MPU interface operates asynchronously, with data
transfers being synchronized by internal logic. All the register locations support read and write operations.
Table 1. Internal Register Map
RS3 RS2 RS1 RS0 REGISTER ADDRESSED BY MPU
L
L
L
L Palette address register – write mode
L
L
L
H Color palette holding register
L
L
H
L Pixel read mask
L
L
H
H Palette address register – read mode
L
H
L
L Reserved
L
H
L
H Reserved
L
H
H
L Reserved
L
H
H
H Reserved
H
L
L
L General control register
H
L
L
H Input clock selection register
H
L
H
L Output clock selection register
H
L
H
H Mux control register
H
H
L
L Palette page register
H
H
L
H Reserved
H
H
H
L Test register
H
H
H
H Reset state
2.2 Color Palette RAM
The color palette RAM is addressed by two internal 8-bit registers, one for reading from the RAM and one
for writing to the RAM. These registers are automatically incremented following a RAM transfer, allowing
the entire palette to be read/written with only one access of the address register. When the address register
increments beyond the last location in RAM, it is reset to the first location (address 0). Although all read and
write accesses to the RAM are asynchronous to SCLK, VCLK, and the dot clock, they are performed within
one dot clock and so do not cause any noticeable disturbance on the display.
The color palette RAM is 24 bits wide for each location (8 bits each for red, green, and blue). If 6-bit mode
is chosen (8/6 = low), the two MSBs are still written to the color palette RAM. However, if they are read back
in the 6-bit mode, the two MSBs are set to 0 to maintain compatibility with the IMSG176/8 and BT476/8 color
palettes. The output MUX shifts the six LSBs to the six MSB positions, fills the two LSBs with 0s, then feeds
the eight bits to the DAC. With the 8/6 pin held low, data on the lowest six bits of the data bus are internally
shifted up by two bits to occupy the upper six bits at the output MUX, and the bottom two bits are then zeroed.
The test register and the ones accumulation register both take data before the output MUX to give the user
the maximum flexibility.
The color palette RAM access methodology is described in the following two sections and is fully compatible
with the IMSG176/8 and BT476/8 color palettes.
2–1