TLC34075-135FN Datasheet, PDF (15/52 Pages) Texas Instruments – Video Interface Palette Data Manual

however, allow for user programming of the SCLK and VCLK outputs (shift and video clocks) via the output
clock selection register. The input/output clock selection registers are shown in Tables 5, 6, and 7.
SCLK is designed to drive the VRAMs directly, and VCLK is designed to work with video control signals such
as BLANK and the SYNCs. While SCLK and VCLK are designed as general-purpose shift clock and video
clock, respectively, they also interface directly with the TMS340x0 GSP family. While SCLK and VCLK can
be selected independently, there is still a relationship between the two. Internally, both SCLK and VCLK are
generated from a common clock counter that increments on the rising edge of the DOTCLK. When VCLK
is enabled and the VCLK and SCLK frequencies are programmed to be the same submultiple of the
DOTCLK frequency, then VCLK and SCLK are in phase. When VCLK is enabled and the VCLK and SCLK
frequencies are programmed to be different submultiples of the DOTCLK frequency, then there are
simultaneous rising edges on the two waveforms at times determined by their frequency ratio
(see Figure 3).
Appendix A discusses the SCLK/VCLK relationship specific to the TMS340x0 GSP.
DOTCLK
VCLK
(DOTCLK/4
as an example)
SCLK
(DOTCLK/2
as an example)
Figure 3. DOTCLK/VCLK/SCLK Relationship
Table 3. Input Clock Selection Register Format
BITS^†
3
2
1
0
FUNCTION ^‡
0
0
0
0 Select CLK0 as clock source^§
0
0
0
1 Select CLK1 as clock source
0
0
1
0 Select CLK2 as clock source
0
0
1
1 Select CLK3 as TTL clock source
0
1
0
0 Select CLK3 as TTL clock source
1
0
0
0 Select CLK3 and CLK3 as ECL clock sources
† _{Register bits 4, 5, 6, and 7 are don’t care bits.}
‡ _{When the clock selection is altered, a minimum 30-ns delay is incurred before the}
new clocks are stabilized and running.
§ _{CLK0 is chosen at power-up to support the VGA pass-through mode.}
2–3