TLC34075-135FN Datasheet, PDF (12/52 Pages) Texas Instruments – Video Interface Palette Data Manual

PIN NAME
NO.
I/O
DESCRIPTION
SFLAG/NFLAG 62
I Split shift register transfer flag or nibble flag input. This pin has two functions.
When the general control register bit 3 = 0 and bit 2 = 1, split shift register
transfer function is enabled and a low-to-high transition on this pin during a
blank sequence initiates an extra SCLK cycle to allow a split shift register
transfer in the VRAMs. When the general control register bit 3 = 1 and
bit 2 = 0, special nibble mode is enabled and this input is sampled at the falling
edge of VCLK. A high value sampled indicates that the next SCLK rising edge
should latch the high nibble of each byte of the pixel data bus; a low value
sampled indicates that the low nibble of each byte of the pixel data bus should
be latched (see Section 2.9). When the general control register bit 3 = 0 and
bit 2 = 0, this pin is ignored. The condition of bit 3 = 1, bit 2 = 1 is not allowed,
and device operation is unpredictable if they are so set.
VCLK
78
O Video clock output. User-programmable output for synchronization of the
TLC34075 to a graphics processor.
VDD
45, 55,
57, 81
Power. All VDD pins must be connected. The analog and digital VDD pins are
connected internally.
VGA<0:7>
65 – 72
I VGA pass-through bus. This bus can be selected as the pixel bus for VGA
pass-through mode. It does not allow for any multiplexing.
VREF
53
Voltage reference for DACs. An internal voltage reference of nominally
1.235 V is designed in. A 0.1-µf ceramic capacitor between this terminal and
GND is recommended for noise filtering using either the internal or an external
reference voltage. The internal reference voltage can be overridden by an
externally supplied voltage. The typical connection is shown in Appendix B.
WR
30
I Write strobe input. A low logic level on this pin initiates a write to the TLC34075
register map. Write transfers are asynchronous. The data written to the
register map is latched on the rising edge of WR (see Figure 3–1).
8/6
64
I DAC resolution selection. This pin is used to select the data bus width (8 or
6 bits) for the DACs and is provided to maintain compatibility with the INMOS
IMSG176/8 color palette. When this pin is at a high logic level, 8-bit bus
transfers are used, with D<7> being the MSB and D<0> the LSB. For 6-bit bus
operation, while the color palette still has the 8-bit information, D<5> shifts to
the bit 7 position, D<0> shifts to the bit 2 position, and the two LSBs are filled
with zeros at the output MUX to the DAC. When read in the 6-bit mode, the
palette-holding register zeroes out the two MSBs.
NOTES: 1. Although leaving unused pins floating will not adversely affect device operation, tying unused pins to ground
lowers power consumption and, thus, is recommended.
2. All digital inputs and outputs are TTL-compatible, unless otherwise noted.
1–6