AMC1210_14 Datasheet, PDF (25/54 Pages) Texas Instruments – Quad Digital Filter for 2nd-Order Delta-Sigma Modulator

AMC1210
www.ti.com.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009
Calibrating the Signal Generator
The Signal Generator unit also must be in phase with the total system for resolver demodulation. This condition
requires a calibration to align the phase of the Signal Generator output to the sinc filter output. The phase
calibration begins when the bit PCAL in the Clock Divider Register is set high. The AMC1210 performs the
calibration by monitoring the polarity of both the output of the signal generator and the sinc filter. Once the
polarities are defined, a demodulation signal is generated with the corresponding phase shift.
The bit PCAL controls demodulation. Initially, it is set high. The AMC1210 then outputs a low on bit PCAL when
the modulation is performed correctly. The microcontroller can monitor the calibration by reading PCAL. The first
calibration attempt will try to calibrate for one period of the Signal Generator. If PCAL stays high after that period,
then calibration has failed. In order to restart calibration, a low must be written to PCAL in order to reset the
PCAL state. Writing a subsequent high starts the calibration over.
Driving a Signal with the Signal Generator
The resolver can be driven directly from the AMC1210. If the bit HBE is set to high, the pins PWM1 and PWM2
are capable of driving 100mA directly into the resolver coils. If bit HBE = 0, the drive capability is lowered.
The pattern generator is enabled by the bit SGE in the Clock Divider Register.
Interrupt Unit
Figure 21 shows the structure of the interrupt unit.
HLT1
COMP1
LLT1
MIE
COMPH1
IEH1
MIE
COMPL1
IEL1
Signal when
Interrupt Register is read
MIE
S Q ^IFH1
R
IEH1
MIE
S Q ^IFL1
R
IEL1
From the
other filter units
From the
watchdog timers
IP
=1
INT Pin
>1
Figure 21. AMC1210 Interrupt Unit
Each comparator output is one interrupt source (COMPHx or COMPLx) creating eight total comparator outputs in
the AMC1210. Each of these eight interrupt sources is stored in a flag register (IFHx or IFLx), if the master
interrupt enable (MIE) and the appropriate interrupt enable (IEHx or IELx) are set to high. This flag register will
be set to high if an interrupt is issued. This flag will be reset if the Interrupt Register is read and the interrupt
source is no longer active. If an interrupt source is still active when the Interrupt Register is read, the appropriate
flag and the INT pin will remain set. Figure 22 illustrates an example of the interrupt behavior depending on the
value of the threshold registers and the corresponding read access to reset the interrupt flag.
If the modulator clock is failing (when the modulator clock is slower than 1/64th of the system clock CLK), a
watchdog timer will set a flag MFx, if the appropriate modulator flag interrupt enable bit (MFIEx) and the master
interrupt enable (MIE) is set. If the modulator clock is still failing when the Interrupt Register is read, the
appropriate flag remains set. The flag clears if the fail condition is no longer true, and the Interrupt Register is
read.
Any of the 12 interrupt bits will activate the interrupt pin INT, if enabled. The polarity of the INT pin can be chosen
with the Interrupt polarity control bit (IP) in the Control Register.
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