AMC1210_14 Datasheet, PDF (24/54 Pages) Texas Instruments – Quad Digital Filter for 2nd-Order Delta-Sigma Modulator

AMC1210
SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com
CONTROL AND INTERRUPT MODULE
The control and interrupt module consists of a Signal Generator unit, a comprehensive interrupt unit and a
register map. The register map contains all control parameters, output data and status bits for the AMC1210. A
detailed description of each register is available in the Register Map section.
Signal Generator Unit
The signal generator (see Figure 20) provides a 5V Pulse Width Modulated (PWM) signal at pin PWM1 and a
complementary signal at PWM2. The output of PWM1 to PWM2 is a 5V differential signal that can be externally
low-pass-filtered to generate a carrier signal with a predefined clock frequency.
The signal generator is a shift register with a length between 1 and 1024. The shift register is programmed
through the Pattern Register (bits SP). On the first write command to the bits SP, the first 16 bits of the shift
register are loaded. Each following write command causes the data in the shift register to shift 16 bits upwards,
and the 16 bits from the Pattern Register are placed in the LSBs of the shift register. For example, if 874 bits of
predefined pattern are to be stored in the shift register, 55 writes to the Pattern Register must be issued (with
MSB first and LSB last), and the value 873 must be written into the bits PC in the Control Register.
PATTERN REGISTER
BIT 15
BIT 0
SHIFT REGISTER
WORD 63
WORD 0
DIRECTION OF DATA OUTPUT FLOW
DIRECTION OF DATA SHIFT WHEN LOADING
Figure 20. AMC1210 Signal Generator Unit
The output data rate of the signal generator is programmed with the Clock Divider Register (bits SD). The output
data rate can be selected to be an integer division of the CLK rate. For example, if the CLK pin is operating at
40MHz with the bits SD = 4, the bit rate of the signal generator is 10MHz. The length of the pattern can be
programmed with the Control Register (bits PC). A length can be chosen between 1 and 1024 bits. This signal is
designed for use as the carrier frequency in resolver applications, where proper demodulation requires a
completely synchronous clock to the carrier timing.
24
Submit Documentation Feedback
Product Folder Link(s): AMC1210
Copyright © 2006–2009, Texas Instruments Incorporated