AMC1210_14 Datasheet, PDF (16/54 Pages) Texas Instruments – Quad Digital Filter for 2nd-Order Delta-Sigma Modulator

AMC1210
SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com
Control Unit
The control unit translates the modulator input data and the corresponding clock so that it can be used by the
AMC1210. Four input options are available, depending on the mode of the modulator. These options are
selected through the bits MOD1 and MOD0 in the Control Parameter Register. Table 6 describes each input
mode. A detailed diagram of the timing of each of these modes can be found in the Timing Characteristics
section; see Figure 1.
MODULATOR MODE
0
1
2
3
MOD1
0
0
1
1
Table 6. Interface Modes
MOD0
0
1
0
1
DESCRIPTION
The modulator clock is running with the modulator data rate. The modulator
data is strobed at every rising edge of the modulator clock.
The modulator clock is running with half of the modulator data rate. The
modulator data is strobed at every edge of the modulator clock.
The modulator clock is off and the modulator data is Manchester-encoded.
The modulator clock is running with double of the modulator data rate. The
modulator data is strobed at every other positive modulator clock edge.
In Modulator Mode 2, the data is Manchester-encoded. An automatic calibration is continuously performed to
achieve optimum decoding performance. The status of this calibration can be checked in the Control Parameter
Register bits MS10–MS0 and in the Status Register bits MALx and MAFx. The clock input CLKx is ignored in this
mode.
Input Clocking
The filter module clock is separate from the system clock (except when using Modulator Mode 3). This design
permits the filter module to run asynchronously from the control module, allowing two different speeds for input
data and control block timing. The clock setup is different for each input mode. See Table 7.
INPUT MODE
0
1
2
3
Table 7. Clock Operation in Each Interface Mode
CLOCK FUNCTIONALITY
The clock for the filter module is fed by the CLKx input, which can be either external or driven by the
modulator. The frequency is the same.
Each edge of CLKx generates a pulse, which clocks the filter module.
The clock for the filter module is generated by the Manchester decoder.
The clock source is the system clock, from the CLK pin. This clock can be divided down by a
programmed number between 1 and 8 by bits MD2–MD0 in the Clock Divider Register. This clock can
also be fed to the CLKx pin to drive the modulator clock if the bit CD in the Control Parameter Register
is set to '1'.
Note that as long as the input data is clocked in correctly, all of the filter module functions (sinc filter unit,
comparator unit, etc.) will be clocked at the same rate.
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