AMC1210_14 Datasheet, PDF (10/54 Pages) Texas Instruments – Quad Digital Filter for 2nd-Order Delta-Sigma Modulator

AMC1210
SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com
PARALLEL MODE 3
TIMING CHARACTERISTICS⁽¹⁾
Over recommended operating free-air temperature range at –40°C to +125°C, DVDD = +5V, and BVDD = +2.7V, unless otherwise noted.
PARAMETER ⁽²⁾
t_w1
CS low width
t_w2
CS high width
t_d1
Delay time from WR low to CS low
t_d2
Delay time from ALE high to CS high
t_d3
Delay time from RD high to CS high
t_d4
Delay time from CS low to RD low
t_w3
RD low width
t_w4
RD high width
t_w5
ALE low width
t_d5
Delay time from ALE high to RD low
t_su1
Setup time from address valid to ALE high
t_h1
Hold time from ALE high to address invalid
t_su2
Setup time from data valid to RD high
t_h2
Hold time from RD high to data invalid
t_d6
Delay time from RD low to data valid
t_d7
Delay time from RD high to databus in tristate
t_d8
Delay time from WR high to CS low
MIN
MAX
UNIT
40
ns
5
ns
5
ns
5
ns
5
ns
3
ns
10
ns
30
ns
6
ns
10
ns
5
ns
5
ns
5
ns
5
ns
30
ns
0
10
ns
5
ns
(1) All input signals are specified with t_R = t_F = 5ns (10% to 90% of BVDD) and timed from a voltage level of (V_IL + V_IH)/2.
(2) t_w2 is obsolete if CS stays low between the RD and ALE pulses.
Parallel mode 3, write access
CS
RD
WR
ALE
AD(7:0)
Internal address
t_w1
t_d1
t_w2
t_d2
t_d3
t_d4
t_w4
t_w5
t_d5
t_su1
t_h1
ADDR
ADDR
t_su2
t_h2
MSB
LSB
Parallel mode 3, read access
t_w3
MSB
ADDR+1
CS
RD
WR
ALE
AD(7:0)
Internal address
t_d8
ADDR
ADDR
MSB
t_d6
t_d7
LSB
MSB
ADDR+1
Figure 6. Parallel Mode 3 Timing
10
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