MSP430FR6979 Datasheet, PDF (22/163 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR6979, MSP430FR69791, MSP430FR6977
MSP430FR6928, MSP430FR6927, MSP430FR69271
SLAS797A – AUGUST 2014 – REVISED MARCH 2015
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Table 4-2. MSP430FR692x(1) Signal Descriptions (continued)
TERMINAL
NAME
PM
RGC
NO. Seg.
General-purpose digital I/O
DESCRIPTION
PJ.2/TMS/ACLK/SROSCOFF
23
Test mode select
ACLK output (divided by 1, 2, 4, or 8)
Low-power debug: CPU Status register OSCOFF
General-purpose digital I/O
PJ.3/TCK/COUT/SRCPUOFF
24
Test clock
Comparator output
Low-power debug: CPU Status register CPUOFF
General-purpose digital I/O
P3.3/TA1.1/TB0CLK/Sx
Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output
25 S25
Timer_B TB0 clock signal TB0CLK input
LCD segment output (segment number is package specific)
General-purpose digital I/O
P3.4/UCA1SIMO/UCA1TXD/
TB0.0/Sx
USCI_A1: Slave in, master out (SPI mode)
26 S24 USCI_A1: Transmit data (UART mode)
Timer_B TB0 CCR0 capture: CCI0A input, compare: Out0 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
P3.5/UCA1SOMI/UCA1RXD/
TB0.1/Sx
USCI_A1: Slave out, master in (SPI mode)
27 S23 USCI_A1: Receive data (UART mode)
Timer_B TB0 CCR1 capture: CCI1A input, compare: Out1 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
P3.6/UCA1CLK/TB0.2/Sx
USCI_A1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
28 S22
Timer_B TB0 CCR2 capture: CCI2A input, compare: Out2 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
P3.7/UCA1STE/TB0.3/Sx
USCI_A1: Slave transmit enable (SPI mode)
29 S21
Timer_B TB0 CCR3 capture: CCI3B input, compare: Out3 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
P2.3/UCA0STE/TB0OUTH/Sx
USCI_A0: Slave transmit enable (SPI mode)
30 S20
Switch all PWM outputs high impedance input - Timer_B TB0
LCD segment output (segment number is package specific)
General-purpose digital I/O
USCI_A0: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
P2.2/UCA0CLK/TB0.4/RTCCLK/Sx 31 S19 Timer_B TB0 CCR4 capture: CCI4B input, compare: Out4 output
RTC clock output for calibration
LCD segment output (segment number is package specific)
22
Terminal Configuration and Functions
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MSP430FR69271