AM3517_14 Datasheet, PDF (198/223 Pages) Texas Instruments – ARM Microprocessors

AM3517, AM3505
SPRS550E – OCTOBER 2009 – REVISED MARCH 2013
www.ti.com
Table 6-130. MMC/SD/SDIO Timing Requirements SD Identification Mode^{(1) (2) (3)(4)} (continued)
NO.
HSSD4/SD4
t_{su(CLKIH-CMDIV)}
MMC/SD/SDIO Interface 3
HSSD3/SD3
t_{su(CMDV-CLKIH)}
HSSD4/SD4
t_{su(CLKIH-CMDIV)}
PARAMETER
Hold time, mmc2_cmd valid after mmc2_clk rising
clock edge
1.8V, 3.3V
MIN
MAX
1249.2
Setup time, mmc3_cmd valid before mmc3_clk rising
clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising
clock edge
1198.4
1249.2
UNIT
ns
ns
ns
Table 6-131. MMC/SD/SDIO Switching Characteristics SD Identification Mode⁽¹⁾⁽²⁾
NO.
PARAMETER
1.8V, 3.3V
MIN
MAX
SD Identification Mode
HSSD1/SD1
t_c(clk)
HSSD2/SD2
t_W(clkH)
HSSD2/SD2
t_W(clkL)
t_dc(clk)
t_j(clk)
MMC/SD/SDIO Interface 1
Cycle time, output clk period
Typical pulse duration, output clk high
Typical pulse duration, output clk low
Duty cycle error, output clk
Jitter standard deviation, output clk
X ⁽³⁾*PO ⁽⁴⁾
Y ⁽⁵⁾*PO⁽⁴⁾
2500
125
200
t_r(clk)
Rise time, output clk
10
t_f(clkH)
Fall time, output clk
10
t_r(clkL)
Rise time, output data
10
t_f(clk)
Fall time, output data
10
HSSD5/SD5
t_d(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to mmc1_cmd
6.3
2492.7
transition
MMC/SD/SDIO Interface 2
t_r(clk)
Rise time, output clk
10
t_f(clkH)
Fall time, output clk
10
t_r(clkL)
Rise time, output data
10
t_f(clk)
Fall time, output data
10
HSSD5/SD5
t_d(CLKOH-CMD)
Delay time, mmc2_clk rising clock edge to mmc2_cmd
6.3
2492.7
transition
MMC/SD/SDIO Interface 3
t_r(clk)
Rise time, output clk
10
t_f(clkH)
Fall time, output clk
10
t_r(clkL)
Rise time, output data
10
t_f(clk)
Fall time, output data
10
HSSD5/SD5
t_d(CLKOH-CMD)
Delay time, mmc3_clk rising clock edge to mmc3_cmd
6.3
2492.7
transition
(1) Corresponding figures showing timing parameters are common with other interface modes (see SD and HS SD modes).
(2) The jitter probability density can be approximated by a Gaussian function.
(3) The X parameter is defined as shown below.
(4) PO = output clk period in ns.
(5) The Y parameter is defined as shown below.
UNIT
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKD
1 or Even
Odd
Table 6-132. X Parameter
X
0.5
(trunc[CLKD/2]+1)/CLKD
198 Timing Requirements and Switching Characteristics
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