AM3517_14 Datasheet, PDF (196/223 Pages) Texas Instruments – ARM Microprocessors

AM3517, AM3505
SPRS550E – OCTOBER 2009 – REVISED MARCH 2013
www.ti.com
6.6.11.2 I²C High-Speed Mode
Table 6-127. I²C High-Speed Mode Timings^{(1) (2)}
1.8V, 3.3V
NO.
PARAMETER
UNIT
MIN
MAX
f_SCL
I1
t_w(SCLH)
I2
t_w(SCLL)
I3
t_{su(SDAV-SCLH)}
I4
t_h(SCLHSDAV)
I5
t_{su(SDAL-SCLH)}
Clock frequency, i2cX_scl
Pulse duration, i2cX_scl high
Pulse duration, i2cX_scl low
3.4
60 ⁽³⁾
160 ⁽³⁾
Setup time, i2cX_sda valid before i2cX_scl active level
10
Hold time, i2cX_sda valid after i2cX_scl active level
70
Setup time, i2cX_scl high after i2cX_sda low
160
(for a START⁽⁴⁾ condition or a repeated START
condition)
MHz
s
s
ns
s
s
I6
t_h(SCLHSDAH)
Hold time, i2cX_sda low level after i2cX_scl high level
160
s
(STOP condition)
I7
t_{h(SCLHRSTART)}
Hold time, i2cX_sda low level after i2cX_scl high level
160
ns
(for a repeated START condition)
t_R(SCL)
t_R(SCL)
Rise time, i2cX_scl
10
40
ns
Rise time, i2cX_scl after a repeated START condition
10
80
ns
and after a bit acknowledge
t_F(SCL)
t_R(SDA)
t_F(SDA)
Fall time, i2cX_scl
Rise time, i2cX_sda
Fall time, i2cX_sda
10
40
ns
10
80
ns
10
80
ns
(1) In i2cX, X is equal to 1, 2, or 3.
(2) The device provides (via the I²C bus) a hold time of at least 300 ns for the i2cx_sda signal (refer to the fall and rise time of i2cx_scl) to
bridge the undefined region of the falling edge of i2cx_scl.
(3) HS-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. t_w(SCLL) > 2 t_w(SCLH).
(4) After this time, the first clock is generated.
i2cX_sda
i2cX_scl
START REPEAT
I5
I6
I1
I2
I3
I4
Figure 6-65. I²C High-Speed Mode(1) (2) (3)
(1) HS-mode master devices generate a serial clock signal with a high-to-low ratio of 1 to 2. t_w(SCLL) > 2 x t_w(SCLH).
(2) In i2cX, X is equal to 1, 2, or 3.
(3) After this time, the first clock is generated.
STOP
I7
030-094
Table 6-128. Correspondence Standard vs. TI Timing References
AM3517/05
STANDARD-I²C
S/F Mode
HS Mode
f_SCL
F_SCL
I1
t_w(SCLH)
T_HIGH
I2
t_w(SCLL)
T_LOW
I3
t_{su(SDAV-SCLH)}
T_SU;DAT
I4
t_h(SCLH-SDAV)
T_SU;DAT
I5
t_{su(SDAL-SCLH)}
T_SU;STA
I6
t_h(SCLH-SDAH)
T_HD;STA
I7
t_{h(SCLH-RSTART)}
T_SU;STO
I8
t_w(SDAH)
T_BUF
F_SCLH
T_HIGH
T_LOW
T_SU;DAT
T_SU;DAT
T_SU;STA
T_HD;STA
T_SU;STO
196 Timing Requirements and Switching Characteristics
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