AM3517_14 Datasheet, PDF (127/223 Pages) Texas Instruments – ARM Microprocessors

AM3517, AM3505
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GPMC_FCLK
gpmc_ncsx
GNF1
SPRS550E – OCTOBER 2009 – REVISED MARCH 2013
GNF6
gpmc_nbe0_cle
gpmc_nadv_ale
GNF7
GNF8
gpmc_noe
gpmc_nwe
gpmc_a[16:1]_d[15:0]
GNF0
GNF9
GNF3
Address
GNF4
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
Figure 6-14. GPMC/NAND Flash – Address Latch Cycle Timing
030-033
GPMC_FCLK
GNF12
gpmc_ncsx
GNF10
GNF15
gpmc_nbe0_cle
gpmc_nadv_ale
gpmc_noe
gpmc_a[16:1]_d[15:0]
GNF13
GNF14
DATA
gpmc_waitx
030-034
Figure 6-15. GPMC/NAND Flash – Data Read Cycle Timing(1) (2) (3)
(1) The GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data is internally sampled by active functional clock
edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(3) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 ,1, 2, or 3.
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Timing Requirements and Switching Characteristics 127
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