AM3517_14 Datasheet, PDF (129/223 Pages) Texas Instruments – ARM Microprocessors

AM3517, AM3505
www.ti.com
SPRS550E – OCTOBER 2009 – REVISED MARCH 2013
6.4.2 SDRAM Controller (SDRC)
The SDRC is a dedicated interface to DDR2/LPDDR1 SDRAM that performs the following functions:
• Buffering of input image data from sensors or video sources
• Intermediate buffering for processing/resizing of image data in the VPFE
• Numerous OSD display buffers
• Intermediate buffering for large raw Bayer data image files while performing image processing
functions
• Buffering for intermediate data while performing video encode and decode functions
• Storage of executable code for the ARM
The main features of the controller are:
• Open Core Protocol 2.2 (OCP) compliant [7].
• Supports JEDEC standard compliant DDR2 [2] and LPDDR1 [4] devices.
– SDRAM address range over 2 chip selects.
– Supports following data bus widths:
OCP Data Bus Width SDRAM Data Bus Width
64 and 128-Bit
16, 32, and 64-Bit
– Supports following CAS latencies:
SDRAM Type
CAS Latencies
DDR2
2, 3, 4, 5, and 6
LPDDR1
2 and 3
– Supports following number of internal banks:
SDRAM Type
Internal Banks
DDR2
1, 2, 4, and 8
LPDDR1
1, 2, and 4
– Supports 256, 512, 1024, and 2048-word page sizes.
– Supports following burst lengths:
SDRAM Type
Burst Length
DDR2
8 (4 not supported)
LPDDR1
8 (2 and 4 not supported)
– Supports sequential burst type.
– SDRAM auto initialization from reset or configuration change.
– Supports Bank Interleaving across both the chip selects.
– Supports Clock Stop mode for LPDDR1 for low power.
– Supports Self Refresh and Precharge Power-Down modes for low power.
– Supports Partial Array Self Refresh and Temperature Controlled Self Refresh modes for low power
in LPDDR1.
– Temperature Controlled Self Refresh is only supported for mobile SDRAM having on-chip
temperature sensor.
– Supports ODT on DDR2.
– Supports prioritized refresh.
– Programmable SDRAM refresh rate and backlog counter.
– Programmable SDRAM timing parameters.
– Supports only little endian.
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Timing Requirements and Switching Characteristics 129
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